diff options
| author | Frank Chang <frank.chang@sifive.com> | 2022-01-18 09:45:14 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 32e579b8c510f0c8d7023d87b0cfacf782cb4a62 (patch) | |
| tree | ff7e162e9591c021e7583c05afea7c30e63ea611 /target/riscv/cpu.c | |
| parent | bfefe406b7666bfc624bf54820aa14bd43838dc5 (diff) | |
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f3d733db4..ef269378de 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -609,8 +609,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { - error_setg(errp, "Zve64f extension depends upon RVF."); + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); return; } if (cpu->cfg.ext_j) { |