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authorWeiwei Li <liweiwei@iscas.ac.cn>2023-02-24 12:08:51 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 17:28:17 -0800
commit0af3f115e68ea9b46fe56fa7af554c61a966a23c (patch)
tree063c09bb8d85218e197347e7393fdd66a85e85d6 /target/riscv/cpu.c
parent7a6613da99ccb0a80adda550722df387736d77da (diff)
target/riscv: Add *envcfg.HADE related check in address translation
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during single-stage address translation. When the hypervisor extension is implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled during G-stage address translation. Set *envcfg.HADE default true for backward compatibility. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/cpu.c')
-rw-r--r--target/riscv/cpu.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c8580f0c80..32cb297cfe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj)
env->bins = 0;
env->two_stage_lookup = false;
- env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
+ env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
+ env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {