diff options
| author | Michael Clark <mjc@sifive.com> | 2019-05-17 15:11:06 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-23 23:44:41 -0700 |
| commit | cbf5827693addaff4e4d2102afedbf078a204eb2 (patch) | |
| tree | e857c066240d7706ccd11e822d53aefdd049faec /target/riscv/cpu.c | |
| parent | 49db9fa1fd7c252596b53cf80876e06f407d09ed (diff) | |
target/riscv: Implement riscv_cpu_unassigned_access
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.
Signed-off-by: Michael Clark <mjc@sifive.com>
[Changes by AF:
- Squash two patches and rewrite commit message
- Set baddr to the access address
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0632ac08cf..5b9fae608c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY + cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif |