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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2020-07-01 23:24:49 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-02 09:19:32 -0700 |
| commit | ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 (patch) | |
| tree | 4ec5715de24553e6f3a9c82e8e9e29586b4a267a /target/riscv/cpu-param.h | |
| parent | 70b78d4e71494c90d2ccb40381336bc9b9a22f79 (diff) | |
target/riscv: add vector extension field in CPURISCVState
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu-param.h')
0 files changed, 0 insertions, 0 deletions