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authorNikunj A Dadhania <nikunj@linux.vnet.ibm.com>2017-01-06 11:44:54 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2017-01-31 10:10:14 +1100
commit9eceae320e7300473b5eb20c160c1730714f1692 (patch)
treefa8de8d24b5519f02a3cb6cf15ee2f93e155a3f3 /target/ppc
parent08e149869e4c391f7006c3621cfbe0945a19b4dd (diff)
target-ppc: Add xsxexpqp instruction
xsxexpqp: VSX Scalar Extract Exponent Quad Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc')
-rw-r--r--target/ppc/translate/vsx-impl.inc.c15
-rw-r--r--target/ppc/translate/vsx-ops.inc.c1
2 files changed, 16 insertions, 0 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 33ca1772c9..228e2a5814 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1224,6 +1224,21 @@ static void gen_xsxexpdp(DisasContext *ctx)
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
}
+
+static void gen_xsxexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+ TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(xth, xbh, 48);
+ tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_movi_i64(xtl, 0);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 85d3b7d164..87f1852978 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,6 +115,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),