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authorPeter Maydell <peter.maydell@linaro.org>2019-06-14 11:44:57 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-17 15:15:06 +0100
commit1120827fa182f0e76226df7ffe7a86598d1df54f (patch)
tree35f39f957b3609984733a4daf3450af639eb2aba /target/ppc/user_only_helper.c
parent83655223ac6143a563e981906ce13fd6f2cfbefd (diff)
target/arm: Only implement doubles if the FPU supports them
The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190614104457.24703-3-peter.maydell@linaro.org
Diffstat (limited to 'target/ppc/user_only_helper.c')
0 files changed, 0 insertions, 0 deletions