diff options
| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2016-11-23 17:07:15 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-01-31 10:10:12 +1100 |
| commit | 5cb091a4fd434ae29fd329308dc2cb3d78a068e6 (patch) | |
| tree | 3b0b260eee046b200802a4d82c70a477fae0ab57 /target/ppc/translate/vsx-impl.inc.c | |
| parent | be0a4faf35fa49d22dfd6a11ed858610881affde (diff) | |
target-ppc: implement lxsd and lxssp instructions
lxsd: Load VSX Scalar Dword
lxssp: Load VSX Scalar Single
Moreover, DS-Form instructions shares the same primary opcode, bits
30:31 are used to decode the instruction. Use a common routine to decode
primary opcode(0x39) - ds-form instructions and branch-out depending on
bits 30:31.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate/vsx-impl.inc.c')
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index ed9588ebfe..1d7cd23b4b 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -190,6 +190,27 @@ static void gen_lxvb16x(DisasContext *ctx) tcg_temp_free(EA); } +#define VSX_LOAD_SCALAR_DS(name, operation) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \ + \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_imm_index(ctx, EA, 0x03); \ + gen_qemu_##operation(ctx, xth, EA); \ + /* NOTE: cpu_vsrl is undefined */ \ + tcg_temp_free(EA); \ +} + +VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) +VSX_LOAD_SCALAR_DS(lxssp, ld32fs) + #define VSX_STORE_SCALAR(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ |