diff options
| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2017-01-06 11:44:56 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-01-31 10:10:14 +1100 |
| commit | 29f8ddb72fb689f08deecc61a42f66eabd10f361 (patch) | |
| tree | 7c2f234246236425c05cd1aca481c33926b93d04 /target/ppc/translate/vsx-impl.inc.c | |
| parent | 05538220acaad3c7e8e438221fe97e483b451637 (diff) | |
target-ppc: Add xsxsigqp instructions
xsxsigqp: VSX Scalar Extract Significand Quad Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate/vsx-impl.inc.c')
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index c6f2208e22..33e934feee 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1268,6 +1268,35 @@ static void gen_xsxsigdp(DisasContext *ctx) tcg_temp_free_i64(nan); } +static void gen_xsxsigqp(DisasContext *ctx) +{ + TCGv_i64 t0, zr, nan, exp; + TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); + TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32); + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + exp = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + zr = tcg_const_i64(0); + nan = tcg_const_i64(32767); + + tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48); + tcg_gen_andi_i64(exp, exp, 0x7FFF); + tcg_gen_movi_i64(t0, 0x0001000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + tcg_gen_andi_i64(xth, cpu_vsrh(rB(ctx->opcode) + 32), 0x0000FFFFFFFFFFFF); + tcg_gen_or_i64(xth, xth, t0); + tcg_gen_mov_i64(xtl, cpu_vsrl(rB(ctx->opcode) + 32)); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(exp); + tcg_temp_free_i64(zr); + tcg_temp_free_i64(nan); +} #endif #undef GEN_XX2FORM |