target/ppc: Drop tcg_temp_free

Translators are no longer required to free tcg temporaries.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 0 insertions, 283 deletions

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4c8db92168..df324fc7ff 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -266,8 +266,6 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
     t0 = tcg_const_i32(excp);
     t1 = tcg_const_i32(error);
     gen_helper_raise_exception_err(cpu_env, t0, t1);
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -282,7 +280,6 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
     gen_update_nip(ctx, ctx->cia);
     t0 = tcg_const_i32(excp);
     gen_helper_raise_exception(cpu_env, t0);
-    tcg_temp_free_i32(t0);
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -294,7 +291,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
     gen_update_nip(ctx, nip);
     t0 = tcg_const_i32(excp);
     gen_helper_raise_exception(cpu_env, t0);
-    tcg_temp_free_i32(t0);
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -341,7 +337,6 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
         gen_load_spr(t0, SPR_BOOKE_DBSR);
         tcg_gen_ori_tl(t0, t0, dbsr);
         gen_store_spr(SPR_BOOKE_DBSR, t0);
-        tcg_temp_free(t0);
         return POWERPC_EXCP_DEBUG;
     } else {
         return POWERPC_EXCP_TRACE;
@@ -393,7 +388,6 @@ static void spr_load_dump_spr(int sprn)
 #ifdef PPC_DUMP_SPR_ACCESSES
     TCGv_i32 t0 = tcg_const_i32(sprn);
     gen_helper_load_dump_spr(cpu_env, t0);
-    tcg_temp_free_i32(t0);
 #endif
 }
 
@@ -408,7 +402,6 @@ static void spr_store_dump_spr(int sprn)
 #ifdef PPC_DUMP_SPR_ACCESSES
     TCGv_i32 t0 = tcg_const_i32(sprn);
     gen_helper_store_dump_spr(cpu_env, t0);
-    tcg_temp_free_i32(t0);
 #endif
 }
 
@@ -437,7 +430,6 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
     TCGv t0 = tcg_temp_new();
     tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
     spr_store_dump_spr(sprn);
 #else
     spr_write_generic(ctx, sprn, gprn);
@@ -452,8 +444,6 @@ void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
     tcg_gen_and_tl(t0, t0, t1);
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
 }
 
 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
@@ -483,9 +473,6 @@ void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
         tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
         tcg_gen_or_tl(dst, dst, t0);
     }
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    tcg_temp_free(t2);
 }
 
 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
@@ -687,28 +674,24 @@ void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 /* DBAT0U...DBAT7U */
@@ -731,28 +714,24 @@ void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 
 /* SDR1 */
@@ -784,7 +763,6 @@ void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
     TCGv t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
-    tcg_temp_free(t0);
 }
 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
 {
@@ -855,7 +833,6 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
     TCGv t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
     gen_helper_store_40x_pid(cpu_env, t0);
-    tcg_temp_free(t0);
 }
 
 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
@@ -878,7 +855,6 @@ void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
     TCGv t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
     gen_store_spr(SPR_PIR, t0);
-    tcg_temp_free(t0);
 }
 #endif
 
@@ -888,7 +864,6 @@ void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
     TCGv_i32 t0 = tcg_temp_new_i32();
     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
-    tcg_temp_free_i32(t0);
 }
 
 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
@@ -896,7 +871,6 @@ void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
     TCGv_i32 t0 = tcg_temp_new_i32();
     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
-    tcg_temp_free_i32(t0);
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -908,7 +882,6 @@ void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
 }
 
 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
@@ -933,7 +906,6 @@ void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
 }
 #endif
 
@@ -968,10 +940,6 @@ void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_or_tl(t0, t0, t2);
     gen_store_spr(SPR_AMR, t0);
     spr_store_dump_spr(SPR_AMR);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    tcg_temp_free(t2);
 }
 
 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
@@ -999,10 +967,6 @@ void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_or_tl(t0, t0, t2);
     gen_store_spr(SPR_UAMOR, t0);
     spr_store_dump_spr(SPR_UAMOR);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    tcg_temp_free(t2);
 }
 
 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
@@ -1030,10 +994,6 @@ void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_or_tl(t0, t0, t2);
     gen_store_spr(SPR_IAMR, t0);
     spr_store_dump_spr(SPR_IAMR);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    tcg_temp_free(t2);
 }
 #endif
 #endif
@@ -1054,7 +1014,6 @@ void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
 
     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
 }
 
 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
@@ -1063,7 +1022,6 @@ void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
 
     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
 }
 
 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
@@ -1073,7 +1031,6 @@ void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_andi_tl(t0, cpu_gpr[gprn],
                     ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
     gen_store_spr(sprn, t0);
-    tcg_temp_free(t0);
 }
 
 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
@@ -1085,7 +1042,6 @@ void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
 {
     TCGv_i32 t0 = tcg_const_i32(sprn);
     gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
-    tcg_temp_free_i32(t0);
 }
 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
 {
@@ -1106,7 +1062,6 @@ void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
     gen_store_spr(SPR_BOOKE_MAS3, val);
     tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
     gen_store_spr(SPR_BOOKE_MAS7, val);
-    tcg_temp_free(val);
 }
 
 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
@@ -1117,8 +1072,6 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
     tcg_gen_shli_tl(mas7, mas7, 32);
     gen_load_spr(mas3, SPR_BOOKE_MAS3);
     tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
-    tcg_temp_free(mas3);
-    tcg_temp_free(mas7);
 }
 
 #endif
@@ -1132,10 +1085,6 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
     TCGv_i32 t3 = tcg_const_i32(cause);
 
     gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
-
-    tcg_temp_free_i32(t3);
-    tcg_temp_free_i32(t2);
-    tcg_temp_free_i32(t1);
 }
 
 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
@@ -1146,10 +1095,6 @@ static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
     TCGv_i32 t3 = tcg_const_i32(cause);
 
     gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
-
-    tcg_temp_free_i32(t3);
-    tcg_temp_free_i32(t2);
-    tcg_temp_free_i32(t1);
 }
 
 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
@@ -1160,9 +1105,6 @@ void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
     gen_load_spr(spr, sprn - 1);
     tcg_gen_shri_tl(spr_up, spr, 32);
     tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
-
-    tcg_temp_free(spr);
-    tcg_temp_free(spr_up);
 }
 
 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
@@ -1172,8 +1114,6 @@ void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
     gen_load_spr(spr, sprn - 1);
     tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
     gen_store_spr(sprn - 1, spr);
-
-    tcg_temp_free(spr);
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -1185,7 +1125,6 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
     tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
     gen_store_spr(sprn, hmer);
     spr_store_dump_spr(sprn);
-    tcg_temp_free(hmer);
 }
 
 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
@@ -1269,8 +1208,6 @@ void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
 
     gen_load_spr(t0, sprn + 16);
     tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
-
-    tcg_temp_free(t0);
 }
 #endif
 
@@ -1447,17 +1384,12 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
     tcg_gen_trunc_tl_i32(t, t0);
     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    tcg_temp_free_i32(t);
 }
 
 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
 {
     TCGv t0 = tcg_const_tl(arg1);
     gen_op_cmp(arg0, t0, s, crf);
-    tcg_temp_free(t0);
 }
 
 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
@@ -1473,15 +1405,12 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
         tcg_gen_ext32u_tl(t1, arg1);
     }
     gen_op_cmp(t0, t1, s, crf);
-    tcg_temp_free(t1);
-    tcg_temp_free(t0);
 }
 
 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
 {
     TCGv t0 = tcg_const_tl(arg1);
     gen_op_cmp32(arg0, t0, s, crf);
-    tcg_temp_free(t0);
 }
 
 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
@@ -1525,10 +1454,6 @@ static void gen_cmprb(DisasContext *ctx)
         tcg_gen_or_i32(crf, crf, src2lo);
     }
     tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
-    tcg_temp_free_i32(src1);
-    tcg_temp_free_i32(src2);
-    tcg_temp_free_i32(src2lo);
-    tcg_temp_free_i32(src2hi);
 }
 
 #if defined(TARGET_PPC64)
@@ -1555,8 +1480,6 @@ static void gen_isel(DisasContext *ctx)
     tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
                        rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
                        cpu_gpr[rB(ctx->opcode)]);
-    tcg_temp_free(zr);
-    tcg_temp_free(t0);
 }
 
 /* cmpb: PowerPC 2.05 specification */
@@ -1580,7 +1503,6 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
     } else {
         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
     }
-    tcg_temp_free(t0);
     if (NARROW_MODE(ctx)) {
         tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
         if (is_isa300(ctx)) {
@@ -1613,7 +1535,6 @@ static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
     }
     tcg_gen_xor_tl(t0, t0, res);
     tcg_gen_extract_tl(ca32, t0, 32, 1);
-    tcg_temp_free(t0);
 }
 
 /* Common add function */
@@ -1642,7 +1563,6 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
                 tcg_gen_add_tl(t0, t0, ca);
             }
             tcg_gen_xor_tl(ca, t0, t1);        /* bits changed w/ carry */
-            tcg_temp_free(t1);
             tcg_gen_extract_tl(ca, ca, 32, 1);
             if (is_isa300(ctx)) {
                 tcg_gen_mov_tl(ca32, ca);
@@ -1656,7 +1576,6 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
                 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
             }
             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
-            tcg_temp_free(zero);
         }
     } else {
         tcg_gen_add_tl(t0, arg1, arg2);
@@ -1674,7 +1593,6 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
 
     if (t0 != ret) {
         tcg_gen_mov_tl(ret, t0);
-        tcg_temp_free(t0);
     }
 }
 /* Add functions with two operands */
@@ -1696,7 +1614,6 @@ static void glue(gen_, name)(DisasContext *ctx)                               \
                      cpu_gpr[rA(ctx->opcode)], t0,                            \
                      ca, glue(ca, 32),                                        \
                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
-    tcg_temp_free(t0);                                                        \
 }
 
 /* add  add.  addo  addo. */
@@ -1722,7 +1639,6 @@ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                      c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
-    tcg_temp_free(c);
 }
 
 static void gen_addic(DisasContext *ctx)
@@ -1769,10 +1685,6 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
         }
         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
     }
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-    tcg_temp_free_i32(t3);
 
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, ret);
@@ -1800,7 +1712,6 @@ static void gen_##name(DisasContext *ctx)                                     \
     TCGv_i32 t0 = tcg_const_i32(compute_ov);                                  \
     gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
-    tcg_temp_free_i32(t0);                                                    \
     if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
     }                                                                         \
@@ -1844,10 +1755,6 @@ static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
         }
         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
     }
-    tcg_temp_free_i64(t0);
-    tcg_temp_free_i64(t1);
-    tcg_temp_free_i64(t2);
-    tcg_temp_free_i64(t3);
 
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, ret);
@@ -1894,19 +1801,13 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
         tcg_gen_rem_i32(t3, t0, t1);
         tcg_gen_ext_i32_tl(ret, t3);
-        tcg_temp_free_i32(t2);
-        tcg_temp_free_i32(t3);
     } else {
         TCGv_i32 t2 = tcg_const_i32(1);
         TCGv_i32 t3 = tcg_const_i32(0);
         tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
         tcg_gen_remu_i32(t3, t0, t1);
         tcg_gen_extu_i32_tl(ret, t3);
-        tcg_temp_free_i32(t2);
-        tcg_temp_free_i32(t3);
     }
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
 }
 
 #define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
@@ -1940,18 +1841,12 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
         tcg_gen_movi_i64(t3, 0);
         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
         tcg_gen_rem_i64(ret, t0, t1);
-        tcg_temp_free_i64(t2);
-        tcg_temp_free_i64(t3);
     } else {
         TCGv_i64 t2 = tcg_const_i64(1);
         TCGv_i64 t3 = tcg_const_i64(0);
         tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
         tcg_gen_remu_i64(ret, t0, t1);
-        tcg_temp_free_i64(t2);
-        tcg_temp_free_i64(t3);
     }
-    tcg_temp_free_i64(t0);
-    tcg_temp_free_i64(t1);
 }
 
 #define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
@@ -1976,8 +1871,6 @@ static void gen_mulhw(DisasContext *ctx)
     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
     tcg_gen_muls2_i32(t0, t1, t0, t1);
     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -1993,8 +1886,6 @@ static void gen_mulhwu(DisasContext *ctx)
     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
     tcg_gen_mulu2_i32(t0, t1, t0, t1);
     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -2010,8 +1901,6 @@ static void gen_mullw(DisasContext *ctx)
     tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
     tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
     tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
 #else
     tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                     cpu_gpr[rB(ctx->opcode)]);
@@ -2044,8 +1933,6 @@ static void gen_mullwo(DisasContext *ctx)
     }
     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -2065,7 +1952,6 @@ static void gen_mulhd(DisasContext *ctx)
     TCGv lo = tcg_temp_new();
     tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-    tcg_temp_free(lo);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -2077,7 +1963,6 @@ static void gen_mulhdu(DisasContext *ctx)
     TCGv lo = tcg_temp_new();
     tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
-    tcg_temp_free(lo);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -2110,9 +1995,6 @@ static void gen_mulldo(DisasContext *ctx)
     }
     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 
-    tcg_temp_free_i64(t0);
-    tcg_temp_free_i64(t1);
-
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
     }
@@ -2148,9 +2030,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
             }
             tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
             tcg_gen_add_tl(t0, t0, inv1);
-            tcg_temp_free(inv1);
             tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
-            tcg_temp_free(t1);
             tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
             if (is_isa300(ctx)) {
                 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
@@ -2162,8 +2042,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
             tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
             tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
             gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
-            tcg_temp_free(zero);
-            tcg_temp_free(inv1);
         } else {
             tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
             tcg_gen_sub_tl(t0, arg2, arg1);
@@ -2190,7 +2068,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
 
     if (t0 != ret) {
         tcg_gen_mov_tl(ret, t0);
-        tcg_temp_free(t0);
     }
 }
 /* Sub functions with Two operands functions */
@@ -2210,7 +2087,6 @@ static void glue(gen_, name)(DisasContext *ctx)                               \
     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
                       cpu_gpr[rA(ctx->opcode)], t0,                           \
                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
-    tcg_temp_free(t0);                                                        \
 }
 /* subf  subf.  subfo  subfo. */
 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
@@ -2234,7 +2110,6 @@ static void gen_subfic(DisasContext *ctx)
     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                       c, 0, 1, 0, 0);
-    tcg_temp_free(c);
 }
 
 /* neg neg. nego nego. */
@@ -2243,7 +2118,6 @@ static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
     TCGv zero = tcg_const_tl(0);
     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
                       zero, 0, 0, compute_ov, Rc(ctx->opcode));
-    tcg_temp_free(zero);
 }
 
 static void gen_neg(DisasContext *ctx)
@@ -2306,7 +2180,6 @@ static void gen_cntlzw(DisasContext *ctx)
     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_clzi_i32(t, t, 32);
     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
-    tcg_temp_free_i32(t);
 
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
@@ -2321,7 +2194,6 @@ static void gen_cnttzw(DisasContext *ctx)
     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_ctzi_i32(t, t, 32);
     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
-    tcg_temp_free_i32(t);
 
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
@@ -2345,7 +2217,6 @@ static void gen_pause(DisasContext *ctx)
     TCGv_i32 t0 = tcg_const_i32(0);
     tcg_gen_st_i32(t0, cpu_env,
                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
-    tcg_temp_free_i32(t0);
 
     /* Stop translation, this gives other CPUs a chance to run */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -2424,7 +2295,6 @@ static void gen_or(DisasContext *ctx)
             tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
             tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
             gen_store_spr(SPR_PPR, t0);
-            tcg_temp_free(t0);
         }
 #if !defined(CONFIG_USER_ONLY)
         /*
@@ -2539,7 +2409,6 @@ static void gen_prtyw(DisasContext *ctx)
     tcg_gen_shri_tl(t0, ra, 8);
     tcg_gen_xor_tl(ra, ra, t0);
     tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
-    tcg_temp_free(t0);
 }
 
 #if defined(TARGET_PPC64)
@@ -2556,7 +2425,6 @@ static void gen_prtyd(DisasContext *ctx)
     tcg_gen_shri_tl(t0, ra, 8);
     tcg_gen_xor_tl(ra, ra, t0);
     tcg_gen_andi_tl(ra, ra, 1);
-    tcg_temp_free(t0);
 }
 #endif
 
@@ -2645,7 +2513,6 @@ static void gen_rlwimi(DisasContext *ctx)
             tcg_gen_trunc_tl_i32(t0, t_rs);
             tcg_gen_rotli_i32(t0, t0, sh);
             tcg_gen_extu_i32_tl(t1, t0);
-            tcg_temp_free_i32(t0);
         } else {
 #if defined(TARGET_PPC64)
             tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
@@ -2658,7 +2525,6 @@ static void gen_rlwimi(DisasContext *ctx)
         tcg_gen_andi_tl(t1, t1, mask);
         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
         tcg_gen_or_tl(t_ra, t_ra, t1);
-        tcg_temp_free(t1);
     }
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, t_ra);
@@ -2702,7 +2568,6 @@ static void gen_rlwinm(DisasContext *ctx)
                 tcg_gen_rotli_i32(t0, t0, sh);
                 tcg_gen_andi_i32(t0, t0, mask);
                 tcg_gen_extu_i32_tl(t_ra, t0);
-                tcg_temp_free_i32(t0);
             }
         } else {
 #if defined(TARGET_PPC64)
@@ -2749,15 +2614,12 @@ static void gen_rlwnm(DisasContext *ctx)
         tcg_gen_andi_i32(t0, t0, 0x1f);
         tcg_gen_rotl_i32(t1, t1, t0);
         tcg_gen_extu_i32_tl(t_ra, t1);
-        tcg_temp_free_i32(t0);
-        tcg_temp_free_i32(t1);
     } else {
 #if defined(TARGET_PPC64)
         TCGv_i64 t0 = tcg_temp_new_i64();
         tcg_gen_andi_i64(t0, t_rb, 0x1f);
         tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
         tcg_gen_rotl_i64(t_ra, t_ra, t0);
-        tcg_temp_free_i64(t0);
 #else
         g_assert_not_reached();
 #endif
@@ -2865,7 +2727,6 @@ static void gen_rldnm(DisasContext *ctx, int mb, int me)
     t0 = tcg_temp_new();
     tcg_gen_andi_tl(t0, t_rb, 0x3f);
     tcg_gen_rotl_tl(t_ra, t_rs, t0);
-    tcg_temp_free(t0);
 
     tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
     if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -2912,7 +2773,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
         tcg_gen_andi_tl(t1, t1, mask);
         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
         tcg_gen_or_tl(t_ra, t_ra, t1);
-        tcg_temp_free(t1);
     }
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, t_ra);
@@ -2941,8 +2801,6 @@ static void gen_slw(DisasContext *ctx)
     t1 = tcg_temp_new();
     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t1);
-    tcg_temp_free(t0);
     tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
@@ -2978,7 +2836,6 @@ static void gen_srawi(DisasContext *ctx)
         t0 = tcg_temp_new();
         tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
-        tcg_temp_free(t0);
         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
         if (is_isa300(ctx)) {
             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
@@ -3009,8 +2866,6 @@ static void gen_srw(DisasContext *ctx)
     t1 = tcg_temp_new();
     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t1);
-    tcg_temp_free(t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
     }
@@ -3030,8 +2885,6 @@ static void gen_sld(DisasContext *ctx)
     t1 = tcg_temp_new();
     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t1);
-    tcg_temp_free(t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
     }
@@ -3064,7 +2917,6 @@ static inline void gen_sradi(DisasContext *ctx, int n)
         t0 = tcg_temp_new();
         tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
-        tcg_temp_free(t0);
         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
         if (is_isa300(ctx)) {
             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
@@ -3123,8 +2975,6 @@ static void gen_srd(DisasContext *ctx)
     t1 = tcg_temp_new();
     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t1);
-    tcg_temp_free(t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
     }
@@ -3296,7 +3146,6 @@ static void glue(gen_, name##x)(DisasContext *ctx)                            \
     EA = tcg_temp_new();                                                      \
     gen_addr_reg_index(ctx, EA);                                              \
     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
-    tcg_temp_free(EA);                                                        \
 }
 
 #define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
@@ -3314,7 +3163,6 @@ static void glue(gen_, name##epx)(DisasContext *ctx)                          \
     EA = tcg_temp_new();                                                      \
     gen_addr_reg_index(ctx, EA);                                              \
     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
-    tcg_temp_free(EA);                                                        \
 }
 
 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
@@ -3342,7 +3190,6 @@ static void glue(gen_, name##x)(DisasContext *ctx)                            \
     EA = tcg_temp_new();                                                      \
     gen_addr_reg_index(ctx, EA);                                              \
     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
-    tcg_temp_free(EA);                                                        \
 }
 #define GEN_STX(name, stop, opc2, opc3, type)                                 \
     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
@@ -3360,7 +3207,6 @@ static void glue(gen_, name##epx)(DisasContext *ctx)                          \
     gen_addr_reg_index(ctx, EA);                                              \
     tcg_gen_qemu_st_tl(                                                       \
         cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop);              \
-    tcg_temp_free(EA);                                                        \
 }
 
 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
@@ -3413,8 +3259,6 @@ static void gen_lmw(DisasContext *ctx)
     t1 = tcg_const_i32(rD(ctx->opcode));
     gen_addr_imm_index(ctx, t0, 0);
     gen_helper_lmw(cpu_env, t0, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
 }
 
 /* stmw */
@@ -3432,8 +3276,6 @@ static void gen_stmw(DisasContext *ctx)
     t1 = tcg_const_i32(rS(ctx->opcode));
     gen_addr_imm_index(ctx, t0, 0);
     gen_helper_stmw(cpu_env, t0, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
 }
 
 /***                    Integer load and store strings                     ***/
@@ -3472,9 +3314,6 @@ static void gen_lswi(DisasContext *ctx)
     t1 = tcg_const_i32(nb);
     t2 = tcg_const_i32(start);
     gen_helper_lsw(cpu_env, t0, t1, t2);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
 }
 
 /* lswx */
@@ -3494,10 +3333,6 @@ static void gen_lswx(DisasContext *ctx)
     t2 = tcg_const_i32(rA(ctx->opcode));
     t3 = tcg_const_i32(rB(ctx->opcode));
     gen_helper_lswx(cpu_env, t0, t1, t2, t3);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-    tcg_temp_free_i32(t3);
 }
 
 /* stswi */
@@ -3520,9 +3355,6 @@ static void gen_stswi(DisasContext *ctx)
     t1 = tcg_const_i32(nb);
     t2 = tcg_const_i32(rS(ctx->opcode));
     gen_helper_stsw(cpu_env, t0, t1, t2);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
 }
 
 /* stswx */
@@ -3543,9 +3375,6 @@ static void gen_stswx(DisasContext *ctx)
     tcg_gen_andi_i32(t1, t1, 0x7F);
     t2 = tcg_const_i32(rS(ctx->opcode));
     gen_helper_stsw(cpu_env, t0, t1, t2);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
 }
 
 /***                        Memory synchronisation                         ***/
@@ -3620,7 +3449,6 @@ static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
         gen_helper_check_tlb_flush_local(cpu_env);
     }
     gen_set_label(l);
-    tcg_temp_free_i32(t);
 }
 #else
 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
@@ -3653,7 +3481,6 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop)
     tcg_gen_mov_tl(cpu_reserve, t0);
     tcg_gen_mov_tl(cpu_reserve_val, gpr);
     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
-    tcg_temp_free(t0);
 }
 
 #define LARX(name, memop)                  \
@@ -3687,10 +3514,6 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
     /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
     tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
     tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
-
-    tcg_temp_free(t);
-    tcg_temp_free(t2);
-    tcg_temp_free(u);
 }
 
 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
@@ -3753,9 +3576,6 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
                                cpu_gpr[(rt + 2) & 31], t0);
             tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
             tcg_gen_mov_tl(dst, t0);
-
-            tcg_temp_free(t0);
-            tcg_temp_free(t1);
         }
         break;
 
@@ -3785,7 +3605,6 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
         /* invoke data storage error handler */
         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
     }
-    tcg_temp_free(EA);
 
     if (need_serial) {
         /* Restart with exclusive lock.  */
@@ -3861,20 +3680,12 @@ static void gen_st_atomic(DisasContext *ctx, MemOp memop)
             tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
             tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
             tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
-
-            tcg_temp_free(ea_plus_s);
-            tcg_temp_free(s2);
-            tcg_temp_free(s);
-            tcg_temp_free(t2);
-            tcg_temp_free(t);
         }
         break;
     default:
         /* invoke data storage error handler */
         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
     }
-    tcg_temp_free(discard);
-    tcg_temp_free(EA);
 }
 
 static void gen_stwat(DisasContext *ctx)
@@ -3899,7 +3710,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop)
     gen_set_access_type(ctx, ACCESS_RES);
     gen_addr_reg_index(ctx, t0);
     tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
-    tcg_temp_free(t0);
 
     t0 = tcg_temp_new();
     tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
@@ -3909,7 +3719,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop)
     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
     tcg_gen_or_tl(t0, t0, cpu_so);
     tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
-    tcg_temp_free(t0);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -3973,13 +3782,11 @@ static void gen_lqarx(DisasContext *ctx)
                                                     ctx->mem_idx));
                 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
             }
-            tcg_temp_free_i32(oi);
             tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
         } else {
             /* Restart with exclusive lock.  */
             gen_helper_exit_atomic(cpu_env);
             ctx->base.is_jmp = DISAS_NORETURN;
-            tcg_temp_free(EA);
             return;
         }
     } else if (ctx->le_mode) {
@@ -3993,7 +3800,6 @@ static void gen_lqarx(DisasContext *ctx)
         gen_addr_add(ctx, EA, EA, 8);
         tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ);
     }
-    tcg_temp_free(EA);
 
     tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
     tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
@@ -4020,7 +3826,6 @@ static void gen_stqcx_(DisasContext *ctx)
     gen_addr_reg_index(ctx, EA);
 
     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
-    tcg_temp_free(EA);
 
     cmp = tcg_temp_new_i128();
     val = tcg_temp_new_i128();
@@ -4032,23 +3837,19 @@ static void gen_stqcx_(DisasContext *ctx)
 
     tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
                                 DEF_MEMOP(MO_128 | MO_ALIGN));
-    tcg_temp_free_i128(cmp);
 
     t0 = tcg_temp_new();
     t1 = tcg_temp_new();
     tcg_gen_extr_i128_i64(t1, t0, val);
-    tcg_temp_free_i128(val);
 
     tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
     tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
     tcg_gen_or_tl(t0, t0, t1);
-    tcg_temp_free(t1);
 
     tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
     tcg_gen_or_tl(t0, t0, cpu_so);
     tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
-    tcg_temp_free(t0);
 
     tcg_gen_br(lab_over);
     gen_set_label(lab_fail);
@@ -4145,7 +3946,6 @@ static void gen_wait(DisasContext *ctx)
         TCGv_i32 t0 = tcg_const_i32(1);
         tcg_gen_st_i32(t0, cpu_env,
                        -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
-        tcg_temp_free_i32(t0);
         /* Stop translation, as the CPU is supposed to sleep from now */
         gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
     }
@@ -4191,7 +3991,6 @@ static void gen_doze(DisasContext *ctx)
     CHK_HV(ctx);
     t = tcg_const_i32(PPC_PM_DOZE);
     gen_helper_pminsn(cpu_env, t);
-    tcg_temp_free_i32(t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 #endif /* defined(CONFIG_USER_ONLY) */
@@ -4207,7 +4006,6 @@ static void gen_nap(DisasContext *ctx)
     CHK_HV(ctx);
     t = tcg_const_i32(PPC_PM_NAP);
     gen_helper_pminsn(cpu_env, t);
-    tcg_temp_free_i32(t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 #endif /* defined(CONFIG_USER_ONLY) */
@@ -4223,7 +4021,6 @@ static void gen_stop(DisasContext *ctx)
     CHK_HV(ctx);
     t = tcg_const_i32(PPC_PM_STOP);
     gen_helper_pminsn(cpu_env, t);
-    tcg_temp_free_i32(t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 #endif /* defined(CONFIG_USER_ONLY) */
@@ -4239,7 +4036,6 @@ static void gen_sleep(DisasContext *ctx)
     CHK_HV(ctx);
     t = tcg_const_i32(PPC_PM_SLEEP);
     gen_helper_pminsn(cpu_env, t);
-    tcg_temp_free_i32(t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 #endif /* defined(CONFIG_USER_ONLY) */
@@ -4255,7 +4051,6 @@ static void gen_rvwinkle(DisasContext *ctx)
     CHK_HV(ctx);
     t = tcg_const_i32(PPC_PM_RVWINKLE);
     gen_helper_pminsn(cpu_env, t);
-    tcg_temp_free_i32(t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
 #endif /* defined(CONFIG_USER_ONLY) */
@@ -4309,7 +4104,6 @@ static void pmu_count_insns(DisasContext *ctx)
         }
 
         gen_set_label(l);
-        tcg_temp_free(t0);
     } else {
         gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
     }
@@ -4324,8 +4118,6 @@ static void pmu_count_insns(DisasContext *ctx)
     gen_load_spr(t0, SPR_POWER_PMC5);
     tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
     gen_store_spr(SPR_POWER_PMC5, t0);
-
-    tcg_temp_free(t0);
   #endif /* #if !defined(CONFIG_USER_ONLY) */
 }
 #else
@@ -4451,8 +4243,6 @@ static void gen_bcond(DisasContext *ctx, int type)
              */
             if (unlikely(!is_book3s_arch2x(ctx))) {
                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
-                tcg_temp_free(temp);
-                tcg_temp_free(target);
                 return;
             }
 
@@ -4480,7 +4270,6 @@ static void gen_bcond(DisasContext *ctx, int type)
                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
             }
         }
-        tcg_temp_free(temp);
     }
     if ((bo & 0x10) == 0) {
         /* Test CR */
@@ -4495,7 +4284,6 @@ static void gen_bcond(DisasContext *ctx, int type)
             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
             tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
         }
-        tcg_temp_free_i32(temp);
     }
     gen_update_cfar(ctx, ctx->cia);
     if (type == BCOND_IM) {
@@ -4512,7 +4300,6 @@ static void gen_bcond(DisasContext *ctx, int type)
             tcg_gen_andi_tl(cpu_nip, target, ~3);
         }
         gen_lookup_and_goto_ptr(ctx);
-        tcg_temp_free(target);
     }
     if ((bo & 0x14) != 0x14) {
         /* fallthrough case */
@@ -4570,8 +4357,6 @@ static void glue(gen_, name)(DisasContext *ctx)                               \
     tcg_gen_andi_i32(t0, t0, bitmask);                                        \
     tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
     tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
-    tcg_temp_free_i32(t0);                                                    \
-    tcg_temp_free_i32(t1);                                                    \
 }
 
 /* crand */
@@ -4724,7 +4509,6 @@ static void gen_tw(DisasContext *ctx)
     t0 = tcg_const_i32(TO(ctx->opcode));
     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                   t0);
-    tcg_temp_free_i32(t0);
 }
 
 /* twi */
@@ -4739,8 +4523,6 @@ static void gen_twi(DisasContext *ctx)
     t0 = tcg_const_tl(SIMM(ctx->opcode));
     t1 = tcg_const_i32(TO(ctx->opcode));
     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
 }
 
 #if defined(TARGET_PPC64)
@@ -4755,7 +4537,6 @@ static void gen_td(DisasContext *ctx)
     t0 = tcg_const_i32(TO(ctx->opcode));
     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                   t0);
-    tcg_temp_free_i32(t0);
 }
 
 /* tdi */
@@ -4770,8 +4551,6 @@ static void gen_tdi(DisasContext *ctx)
     t0 = tcg_const_tl(SIMM(ctx->opcode));
     t1 = tcg_const_i32(TO(ctx->opcode));
     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free_i32(t1);
 }
 #endif
 
@@ -4792,8 +4571,6 @@ static void gen_mcrxr(DisasContext *ctx)
     tcg_gen_shli_i32(dst, dst, 1);
     tcg_gen_or_i32(dst, dst, t0);
     tcg_gen_or_i32(dst, dst, t1);
-    tcg_temp_free_i32(t0);
-    tcg_temp_free_i32(t1);
 
     tcg_gen_movi_tl(cpu_so, 0);
     tcg_gen_movi_tl(cpu_ov, 0);
@@ -4817,8 +4594,6 @@ static void gen_mcrxrx(DisasContext *ctx)
     tcg_gen_or_tl(t1, t1, cpu_ca32);
     tcg_gen_or_tl(t0, t0, t1);
     tcg_gen_trunc_tl_i32(dst, t0);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
 }
 #endif
 
@@ -4853,7 +4628,6 @@ static void gen_mfcr(DisasContext *ctx)
         tcg_gen_shli_i32(t0, t0, 4);
         tcg_gen_or_i32(t0, t0, cpu_crf[7]);
         tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
-        tcg_temp_free_i32(t0);
     }
 }
 
@@ -4950,7 +4724,6 @@ static void gen_mtcrf(DisasContext *ctx)
             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
             tcg_gen_shri_i32(temp, temp, crn * 4);
             tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
-            tcg_temp_free_i32(temp);
         }
     } else {
         TCGv_i32 temp = tcg_temp_new_i32();
@@ -4961,7 +4734,6 @@ static void gen_mtcrf(DisasContext *ctx)
                     tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
             }
         }
-        tcg_temp_free_i32(temp);
     }
 }
 
@@ -5008,9 +4780,6 @@ static void gen_mtmsrd(DisasContext *ctx)
 
     /* Must stop the translation as machine state (may have) changed */
     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
 #endif /* !defined(CONFIG_USER_ONLY) */
 }
 #endif /* defined(TARGET_PPC64) */
@@ -5050,9 +4819,6 @@ static void gen_mtmsr(DisasContext *ctx)
 
     /* Must stop the translation as machine state (may have) changed */
     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
 #endif
 }
 
@@ -5125,8 +4891,6 @@ static void gen_setb(DisasContext *ctx)
     tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
     tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
     tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
-
-    tcg_temp_free_i32(t0);
 }
 #endif
 
@@ -5141,7 +4905,6 @@ static void gen_dcbf(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_qemu_ld8u(ctx, t0, t0);
-    tcg_temp_free(t0);
 }
 
 /* dcbfep (external PID dcbf) */
@@ -5154,7 +4917,6 @@ static void gen_dcbfep(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
-    tcg_temp_free(t0);
 }
 
 /* dcbi (Supervisor only) */
@@ -5173,8 +4935,6 @@ static void gen_dcbi(DisasContext *ctx)
     /* XXX: specification says this should be treated as a store by the MMU */
     gen_qemu_ld8u(ctx, val, EA);
     gen_qemu_st8(ctx, val, EA);
-    tcg_temp_free(val);
-    tcg_temp_free(EA);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5187,7 +4947,6 @@ static void gen_dcbst(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_qemu_ld8u(ctx, t0, t0);
-    tcg_temp_free(t0);
 }
 
 /* dcbstep (dcbstep External PID version) */
@@ -5199,7 +4958,6 @@ static void gen_dcbstep(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
-    tcg_temp_free(t0);
 }
 
 /* dcbt */
@@ -5250,7 +5008,6 @@ static void gen_dcbtls(DisasContext *ctx)
     gen_load_spr(t0, SPR_Exxx_L1CSR0);
     tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
     gen_store_spr(SPR_Exxx_L1CSR0, t0);
-    tcg_temp_free(t0);
 }
 
 /* dcblc */
@@ -5272,8 +5029,6 @@ static void gen_dcbz(DisasContext *ctx)
     tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
     gen_addr_reg_index(ctx, tcgv_addr);
     gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
-    tcg_temp_free(tcgv_addr);
-    tcg_temp_free_i32(tcgv_op);
 }
 
 /* dcbzep */
@@ -5287,8 +5042,6 @@ static void gen_dcbzep(DisasContext *ctx)
     tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
     gen_addr_reg_index(ctx, tcgv_addr);
     gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
-    tcg_temp_free(tcgv_addr);
-    tcg_temp_free_i32(tcgv_op);
 }
 
 /* dst / dstt */
@@ -5326,7 +5079,6 @@ static void gen_icbi(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_icbi(cpu_env, t0);
-    tcg_temp_free(t0);
 }
 
 /* icbiep */
@@ -5337,7 +5089,6 @@ static void gen_icbiep(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_icbiep(cpu_env, t0);
-    tcg_temp_free(t0);
 }
 
 /* Optional: */
@@ -5365,7 +5116,6 @@ static void gen_mfsr(DisasContext *ctx)
     CHK_SV(ctx);
     t0 = tcg_const_tl(SR(ctx->opcode));
     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5381,7 +5131,6 @@ static void gen_mfsrin(DisasContext *ctx)
     t0 = tcg_temp_new();
     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5396,7 +5145,6 @@ static void gen_mtsr(DisasContext *ctx)
     CHK_SV(ctx);
     t0 = tcg_const_tl(SR(ctx->opcode));
     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5412,7 +5160,6 @@ static void gen_mtsrin(DisasContext *ctx)
     t0 = tcg_temp_new();
     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5430,7 +5177,6 @@ static void gen_mfsr_64b(DisasContext *ctx)
     CHK_SV(ctx);
     t0 = tcg_const_tl(SR(ctx->opcode));
     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5446,7 +5192,6 @@ static void gen_mfsrin_64b(DisasContext *ctx)
     t0 = tcg_temp_new();
     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5461,7 +5206,6 @@ static void gen_mtsr_64b(DisasContext *ctx)
     CHK_SV(ctx);
     t0 = tcg_const_tl(SR(ctx->opcode));
     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5477,7 +5221,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
     t0 = tcg_temp_new();
     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5531,7 +5274,6 @@ static void gen_eciwx(DisasContext *ctx)
     gen_addr_reg_index(ctx, t0);
     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
                        DEF_MEMOP(MO_UL | MO_ALIGN));
-    tcg_temp_free(t0);
 }
 
 /* ecowx */
@@ -5544,7 +5286,6 @@ static void gen_ecowx(DisasContext *ctx)
     gen_addr_reg_index(ctx, t0);
     tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
                        DEF_MEMOP(MO_UL | MO_ALIGN));
-    tcg_temp_free(t0);
 }
 
 /* 602 - 603 - G2 TLB management */
@@ -5592,7 +5333,6 @@ static void gen_tlbiva(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5710,8 +5450,6 @@ static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
     } else {
         tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
     }
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
     if (unlikely(Rc) != 0) {
         /* Update Rc0 */
         gen_set_Rc0(ctx, cpu_gpr[rt]);
@@ -5822,7 +5560,6 @@ static void gen_mfdcr(DisasContext *ctx)
     CHK_SV(ctx);
     dcrn = tcg_const_tl(SPR(ctx->opcode));
     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
-    tcg_temp_free(dcrn);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5837,7 +5574,6 @@ static void gen_mtdcr(DisasContext *ctx)
     CHK_SV(ctx);
     dcrn = tcg_const_tl(SPR(ctx->opcode));
     gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
-    tcg_temp_free(dcrn);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -5890,9 +5626,7 @@ static void gen_dcread(DisasContext *ctx)
     gen_addr_reg_index(ctx, EA);
     val = tcg_temp_new();
     gen_qemu_ld32u(ctx, val, EA);
-    tcg_temp_free(val);
     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
-    tcg_temp_free(EA);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -6010,7 +5744,6 @@ static void gen_tlbsx_40x(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
     if (Rc(ctx->opcode)) {
         TCGLabel *l1 = gen_new_label();
         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
@@ -6063,7 +5796,6 @@ static void gen_tlbre_440(DisasContext *ctx)
             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
             gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
                                  t0, cpu_gpr[rA(ctx->opcode)]);
-            tcg_temp_free_i32(t0);
         }
         break;
     default:
@@ -6085,7 +5817,6 @@ static void gen_tlbsx_440(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
-    tcg_temp_free(t0);
     if (Rc(ctx->opcode)) {
         TCGLabel *l1 = gen_new_label();
         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
@@ -6111,7 +5842,6 @@ static void gen_tlbwe_440(DisasContext *ctx)
             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
             gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
                                  cpu_gpr[rS(ctx->opcode)]);
-            tcg_temp_free_i32(t0);
         }
         break;
     default:
@@ -6152,7 +5882,6 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
 
     tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
     gen_helper_booke206_tlbsx(cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -6178,7 +5907,6 @@ static void gen_tlbivax_booke206(DisasContext *ctx)
     t0 = tcg_temp_new();
     gen_addr_reg_index(ctx, t0);
     gen_helper_booke206_tlbivax(cpu_env, t0);
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -6207,8 +5935,6 @@ static void gen_tlbilx_booke206(DisasContext *ctx)
         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
         break;
     }
-
-    tcg_temp_free(t0);
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
@@ -6226,7 +5952,6 @@ static void gen_wrtee(DisasContext *ctx)
     tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
     tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
     gen_ppc_maybe_interrupt(ctx);
-    tcg_temp_free(t0);
     /*
      * Stop translation to have a chance to raise an exception if we
      * just set msr_ee to 1
@@ -6261,7 +5986,6 @@ static void gen_dlmzb(DisasContext *ctx)
     TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
     gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
-    tcg_temp_free_i32(t0);
 }
 
 /* mbar replaces eieio on 440 */
@@ -6298,7 +6022,6 @@ static void gen_maddld(DisasContext *ctx)
 
     tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
     tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
-    tcg_temp_free_i64(t1);
 }
 
 /* maddhd maddhdu */
@@ -6319,9 +6042,6 @@ static void gen_maddhd_maddhdu(DisasContext *ctx)
     }
     tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
                      cpu_gpr[rC(ctx->opcode)], t1);
-    tcg_temp_free_i64(lo);
-    tcg_temp_free_i64(hi);
-    tcg_temp_free_i64(t1);
 }
 #endif /* defined(TARGET_PPC64) */
 
@@ -6672,9 +6392,6 @@ static void gen_brh(DisasContext *ctx)
     tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
     tcg_gen_shli_i64(t1, t1, 8);
     tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
-
-    tcg_temp_free_i64(t1);
-    tcg_temp_free_i64(t2);
 }
 #endif