diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2017-02-24 17:35:50 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-03-01 11:23:39 +1100 |
| commit | e78308fd3959c2694c8c366efdccacdd11997ac8 (patch) | |
| tree | b8af29ed61d05872ac7244b9bf6011f41b985f87 /target/ppc/mmu_helper.c | |
| parent | 8d63351f9f99412fd2b99e2f5a8be2bc87d5670e (diff) | |
target/ppc: Correct SDR1 masking
SDR_64_HTABORG, which indicates the bits of the SDR1 register to use for
the base of a 64-bit machine's hashed page table (HPT) isn't correct. It
includes the top 46 bits of the register, but in fact the top 4 bits must
be zero (according to the ISA v2.07). No actual implementation has
supported close to 2^60 bytes of physical address space, so it's kind of
irrelevant, but we might as well correct this.
In addition, although we checked for bad size values in SDR1, we never
reported an error if entirely invalid bits were set there. Add this check
to ppc_store_sdr1().
Reported-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/mmu_helper.c')
| -rw-r--r-- | target/ppc/mmu_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 3bc80303e9..a1af3d6bf2 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2007,8 +2007,14 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) assert(!cpu->vhyp); #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { + target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE; target_ulong htabsize = value & SDR_64_HTABSIZE; + if (value & ~sdr_mask) { + error_report("Invalid bits 0x"TARGET_FMT_lx" set in SDR1", + value & ~sdr_mask); + value &= sdr_mask; + } if (htabsize > 28) { error_report("Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1", htabsize); |