diff options
| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2017-02-10 16:25:51 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-02-22 11:28:28 +1100 |
| commit | 86cf1e9fe852e5c322968c2c708a7efa8b7be5d9 (patch) | |
| tree | a822ee586b21bab11008149a31eca4871f774375 /target/ppc/mmu_helper.c | |
| parent | 7659ca1a3e22aa298022b1ecb21bf3650a01e814 (diff) | |
target/ppc/POWER9: Add ISAv3.00 MMU definition
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/mmu_helper.c')
| -rw-r--r-- | target/ppc/mmu_helper.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f746f53615..172a305e0f 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: #endif /* defined(TARGET_PPC64) */ env->tlb_need_flush = 0; tlb_flush(CPU(cpu)); @@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, |