diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-26 09:19:11 -0700 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-07-03 09:56:52 +1000 |
| commit | f89ced5f556a06986d362dd41a99dfc4dc960fc1 (patch) | |
| tree | 929f21098327572a94492c9cb024acbb6d9c5ed7 /target/ppc/mem_helper.c | |
| parent | 94bf2658676be00b6f2b4db5d1788122217665b0 (diff) | |
target/ppc: Use atomic store for STQ
Section 1.4 of the Power ISA v3.0B states that this insn is
single-copy atomic. As we cannot (yet) issue 128-bit stores
within TCG, use the generic helpers provided.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/mem_helper.c')
| -rw-r--r-- | target/ppc/mem_helper.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 44a8f3445a..57e301edc3 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -231,6 +231,20 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, env->retxh = int128_gethi(ret); return int128_getlo(ret); } + +void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val = int128_make128(lo, hi); + helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); +} + +void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val = int128_make128(lo, hi); + helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); +} #endif /*****************************************************************************/ |