diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-01-04 07:55:34 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-04 07:55:34 +0100 |
| commit | 6e8b990354d244ad5af40c747fdf3c008962b4e3 (patch) | |
| tree | 0e65c2d0e34eadbadf6ec696446caab29ba850be /target/ppc/machine.c | |
| parent | 93130c8475692b1e52e3d3c3beedc3a79b4562d5 (diff) | |
target/ppc: Cache per-pmc insn and cycle count settings
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handling, "PMC[1-6]" comment]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/machine.c')
| -rw-r--r-- | target/ppc/machine.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 93972df58e..756d8de5d8 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -8,6 +8,7 @@ #include "qapi/error.h" #include "qemu/main-loop.h" #include "kvm_ppc.h" +#include "power8-pmu.h" static void post_load_update_msr(CPUPPCState *env) { @@ -19,6 +20,7 @@ static void post_load_update_msr(CPUPPCState *env) */ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); + pmu_update_summaries(env); } static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) |