diff options
author | Luis Pires <luis.pires@eldorado.org.br> | 2021-10-29 16:24:17 -0300 |
---|---|---|
committer | David Gibson <david@gibson.dropbear.id.au> | 2021-11-09 10:32:52 +1100 |
commit | a23297479cc07812526fb6d9d213392dba555145 (patch) | |
tree | 505dcb741ab105dc05059cf700c6ded0a1ac64ed /target/ppc/insn32.decode | |
parent | c8ef4d1ec0ac395f6e4aac7f6013807db8178547 (diff) |
target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree
Move the following instructions to decodetree:
ddedpd: DFP Decode DPD To BCD
ddedpdq: DFP Decode DPD To BCD Quad
denbcd: DFP Encode BCD To DPD
denbcdq: DFP Encode BCD To DPD Quad
dscli: DFP Shift Significand Left Immediate
dscliq: DFP Shift Significand Left Immediate Quad
dscri: DFP Shift Significand Right Immediate
dscriq: DFP Shift Significand Right Immediate Quad
Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were
moved to decodetree.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-16-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/insn32.decode')
-rw-r--r-- | target/ppc/insn32.decode | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 033bae2b32..65075f0d03 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -81,6 +81,16 @@ &X_bfl bf l:bool ra rb @X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl +&X_tb_sp_rc rt rb sp rc:bool +@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc + +@X_tbp_sp_rc ...... ....0 sp:2 ... ....0 .......... rc:1 &X_tb_sp_rc rt=%x_frtp rb=%x_frbp + +&X_tb_s_rc rt rb s:bool rc:bool +@X_tb_s_rc ...... rt:5 s:1 .... rb:5 .......... rc:1 &X_tb_s_rc + +@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp + &X_frtp_vrb frtp vrb @X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp @@ -93,6 +103,12 @@ %z22_frap 17:4 !function=times_2 @Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap +&Z22_ta_sh_rc rt ra sh rc:bool +@Z22_ta_sh_rc ...... rt:5 ra:5 sh:6 ......... rc:1 &Z22_ta_sh_rc + +%z22_frtp 22:4 !function=times_2 +@Z22_tap_sh_rc ...... ....0 ....0 sh:6 ......... rc:1 &Z22_ta_sh_rc rt=%z22_frtp ra=%z22_frap + &Z23_tab frt fra frb rmc rc:bool @Z23_tab ...... frt:5 fra:5 frb:5 rmc:2 ........ rc:1 &Z23_tab @@ -297,12 +313,24 @@ DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp ### Decimal Floating-Point Format Instructions +DDEDPD 111011 ..... .. --- ..... 0101000010 . @X_tb_sp_rc +DDEDPDQ 111111 ..... .. --- ..... 0101000010 . @X_tbp_sp_rc + +DENBCD 111011 ..... . ---- ..... 1101000010 . @X_tb_s_rc +DENBCDQ 111111 ..... . ---- ..... 1101000010 . @X_tbp_s_rc + DXEX 111011 ..... ----- ..... 0101100010 . @X_tb_rc DXEXQ 111111 ..... ----- ..... 0101100010 . @X_t_bp_rc DIEX 111011 ..... ..... ..... 1101100010 . @X_rc DIEXQ 111111 ..... ..... ..... 1101100010 . @X_tp_a_bp_rc +DSCLI 111011 ..... ..... ...... 001000010 . @Z22_ta_sh_rc +DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc + +DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc +DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc + ## Vector Bit Manipulation Instruction VCFUGED 000100 ..... ..... ..... 10101001101 @VX |