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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2019-06-16 13:37:45 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2019-07-02 09:43:58 +1000
commit8d830485fc551b4ff6f609e4245cf49e63fdf9ff (patch)
tree5d34fd18f143f711dd98425f47e7e1f98a6a8f5e /target/ppc/fpu_helper.c
parent033e1fcd97babd6302fd7e983102966a2cafb95c (diff)
target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c
Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_X1 macro which performs the decode based upon xB at translation time. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190616123751.781-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/fpu_helper.c')
-rw-r--r--target/ppc/fpu_helper.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 902d63b139..5fb43b619e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2236,9 +2236,8 @@ VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
* nbits - number of fraction bits
*/
#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
-void helper_##op(CPUPPCState *env, uint32_t opcode) \
+void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
{ \
- ppc_vsr_t *xb = &env->vsr[xB(opcode)]; \
int i; \
int fe_flag = 0; \
int fg_flag = 0; \
@@ -3258,9 +3257,8 @@ VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
-void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)
+void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
{
- ppc_vsr_t *xb = &env->vsr[xB(opcode)];
uint32_t dcmx, sign, exp;
uint32_t cc, match = 0, not_sp = 0;