diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2019-02-15 17:16:46 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-02-26 09:21:24 +1100 |
| commit | d8ce5fd6643d5c568d6357354c205474e7022602 (patch) | |
| tree | c7e1f7de9e5bb1f1129957e2c0e189fd1ce687e9 /target/ppc/excp_helper.c | |
| parent | f8154fd22bf80b1555bac46119747e899c09d0c9 (diff) | |
target/ppc: Add Hypervisor Virtualization Interrupt on POWER9
This adds support for delivering that exception
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190215161648.9600-9-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/excp_helper.c')
| -rw-r--r-- | target/ppc/excp_helper.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1a2f469a5f..d171a5eb62 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -97,6 +97,9 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, case POWERPC_EXCP_HV_MAINT: *msr |= 0xaull << (63 - 45); break; + case POWERPC_EXCP_HVIRT: + *msr |= 0x9ull << (63 - 45); + break; default: cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", excp); @@ -427,6 +430,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ case POWERPC_EXCP_HV_EMU: + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ srr0 = SPR_HSRR0; srr1 = SPR_HSRR1; new_msr |= (target_ulong)MSR_HVB; @@ -809,7 +813,18 @@ static void ppc_hw_interrupt(CPUPPCState *env) return; } } - /* Extermal interrupt can ignore MSR:EE under some circumstances */ + + /* Hypervisor virtualization interrupt */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) { + /* LPCR will be clear when not supported so this will work */ + bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); + if ((async_deliver || msr_hv == 0) && hvice) { + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HVIRT); + return; + } + } + + /* External interrupt can ignore MSR:EE under some circumstances */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); if (async_deliver || (env->has_hv_mode && msr_hv == 0 && !lpes0)) { |