diff options
| author | Cédric Le Goater <clg@kaod.org> | 2022-01-04 07:55:34 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-04 07:55:34 +0100 |
| commit | dd69d140cedc904f3491c17415f75d753c7f1be4 (patch) | |
| tree | 58687f50b1400139bf5b7bf0683a1c238c8ccf8e /target/ppc/cpu_init.c | |
| parent | c316203c1ee6f9a6c301a0a6767d27cbb6a65c46 (diff) | |
ppc/ppc405: Introduce a store helper for SPR_40x_PID
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/cpu_init.c')
| -rw-r--r-- | target/ppc/cpu_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b5e2fde9ec..9ef9a1a5dd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1454,7 +1454,7 @@ static void register_405_sprs(CPUPPCState *env) /* MMU */ spr_register(env, SPR_40x_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_40x_pid, 0x00000000); spr_register(env, SPR_4xx_CCR0, "CCR0", SPR_NOACCESS, SPR_NOACCESS, |