aboutsummaryrefslogtreecommitdiff
path: root/target/ppc/cpu_init.c
diff options
context:
space:
mode:
authorNicholas Piggin <npiggin@gmail.com>2023-05-22 16:23:21 +1000
committerNicholas Piggin <npiggin@gmail.com>2024-05-24 09:34:40 +1000
commitc9d5aedf40cfa0d68a6a4c020d14f8e6116a369e (patch)
tree7b3e45f92c97f4585ea355265b014287ccdfb4d7 /target/ppc/cpu_init.c
parent4d2b0ad32a593ac24757b66f64efe2fb84161345 (diff)
target/ppc: Implement LDBAR, TTR SPRs
LDBAR, TTR are a Power-specific SPRs. These simple implementations are enough for IBM proprietary firmware for now. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc/cpu_init.c')
-rw-r--r--target/ppc/cpu_init.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 415cc7a4e2..d181adc5f1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5767,6 +5767,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
&spr_access_nop, &spr_write_generic,
&spr_access_nop, &spr_write_generic,
0x00000000);
+ spr_register_hv(env, SPR_LDBAR, "LDBAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_lpar_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_POWER_TTR, "TTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_write_generic,
+ 0x00000000);
#endif
}