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authorNicholas Piggin <npiggin@gmail.com>2023-07-05 22:06:29 +1000
committerDaniel Henrique Barboza <danielhb413@gmail.com>2023-07-07 04:47:49 -0300
commit9cdfd1b9f7eb5ecd1267bbd68330a11dcb8aa8f2 (patch)
tree5f720d103c85d07705f476ed5be333da9853134b /target/ppc/cpu_init.c
parent3401ea3cfe06ab5ab059ae19b662270e1357545e (diff)
target/ppc: SMT support for the HID SPR
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/cpu_init.c')
-rw-r--r--target/ppc/cpu_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 905a59aea9..720aad9e05 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5638,7 +5638,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_core_write_generic,
0x00000000);
spr_register_hv(env, SPR_TSCR, "TSCR",
SPR_NOACCESS, SPR_NOACCESS,