diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-26 09:19:13 -0700 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-07-03 09:56:52 +1000 |
| commit | 14db18997eb29b79f6c538c1a3cd27df259f77a6 (patch) | |
| tree | 3b97f26e281c19a5350d2eaa99f2360d9048743e /target/ppc/cpu.h | |
| parent | 4a9b3c5dd30cfd548d447521d4ef1fdba6f0fcf2 (diff) | |
target/ppc: Remove POWERPC_EXCP_STCX
Always use the gen_conditional_store implementation that uses
atomic_cmpxchg. Make sure and clear reserve_addr across most
interrupts crossing the cpu_loop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
| -rw-r--r-- | target/ppc/cpu.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 973cf44cda..4edcf62cf7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -196,7 +196,6 @@ enum { /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ - POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ }; /* Exceptions error codes */ @@ -994,10 +993,6 @@ struct CPUPPCState { /* Reservation value */ target_ulong reserve_val; target_ulong reserve_val2; - /* Reservation store address */ - target_ulong reserve_ea; - /* Reserved store source register and size */ - target_ulong reserve_info; /* Those ones are used in supervisor mode only */ /* machine state register */ |