diff options
| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2017-03-01 18:12:55 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-03-03 11:30:59 +1100 |
| commit | da82c73a950a99b9d6c1ec3eba3d1d6034effd43 (patch) | |
| tree | a32762131c74fc12796f18d7232f3eabb1764f93 /target/ppc/cpu.h | |
| parent | 07a68f990785a8574c78a36b21cf5165e46f1113 (diff) | |
target/ppc: Rework hash mmu page fault code and add defines for clarity
The hash mmu page fault handling code is responsible for generating ISIs
and DSIs when access permissions cause an access to fail. Part of this
involves setting the srr1 or dsisr registers to indicate what causes the
access to fail. Add defines for the bit fields of these registers and
rework the code to use these new defines in order to improve readability
and code clarity.
While we're here, update what is logged when an access fails to include
information as to what caused to access to fail for debug purposes.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[dwg: Moved constants to cpu.h since they're not MMUv3 specific]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
| -rw-r--r-- | target/ppc/cpu.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 14c286e09a..7c4a1f50b3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -473,11 +473,21 @@ struct ppc_slb_t { #endif #endif +/* DSISR */ +#define DSISR_NOPTE 0x40000000 +/* Not permitted by access authority of encoded access authority */ +#define DSISR_PROTFAULT 0x08000000 +#define DSISR_ISSTORE 0x02000000 +/* Not permitted by virtual page class key protection */ +#define DSISR_AMR 0x00200000 + /* SRR1 error code fields */ +#define SRR1_NOPTE DSISR_NOPTE +/* Not permitted due to no-execute or guard bit set */ #define SRR1_NOEXEC_GUARD 0x10000000 -#define SRR1_PROTFAULT 0x08000000 -#define SRR1_IAMR 0x00200000 +#define SRR1_PROTFAULT DSISR_PROTFAULT +#define SRR1_IAMR DSISR_AMR /* Facility Status and Control (FSCR) bits */ #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ |