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authorRichard Henderson <richard.henderson@linaro.org>2021-03-23 12:43:36 -0600
committerDavid Gibson <david@gibson.dropbear.id.au>2021-05-04 11:41:24 +1000
commitf03de3b44b1053c3c82f41a22ae452d1ecfdd8c5 (patch)
treeca441df0a8df28109c38b5d90e38fcefc3917348 /target/ppc/cpu.h
parentf43520e5b233828bd4d98b4a1300ddb475e7486a (diff)
target/ppc: Put LPCR[GTSE] in hflags
Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
-rw-r--r--target/ppc/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d5f362506a..3c28ddb331 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -596,6 +596,7 @@ enum {
HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */
HFLAGS_HV = 1, /* computed from MSR_HV and other state */
HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
+ HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
HFLAGS_DR = 4, /* MSR_DR */
HFLAGS_IR = 5, /* MSR_IR */
HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */