diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2021-05-01 17:24:35 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 13:12:46 +1000 |
| commit | 526cdce771fa27c37b68fd235ff9f1caa0bdd563 (patch) | |
| tree | 17ecd66691cbeb0e317e767001362a637200a3d0 /target/ppc/cpu-qom.h | |
| parent | 8b7e6b07a46809a75b857d30ae47e697e0f9b724 (diff) | |
target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu-qom.h')
| -rw-r--r-- | target/ppc/cpu-qom.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 118baf8d41..06b6571bc9 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -116,6 +116,8 @@ enum powerpc_excp_t { POWERPC_EXCP_POWER8, /* POWER9 exception model */ POWERPC_EXCP_POWER9, + /* POWER10 exception model */ + POWERPC_EXCP_POWER10, }; /*****************************************************************************/ |