diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 18:42:13 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | 01ec3ec930c90374a8870e99e0da63c17d708d47 (patch) | |
| tree | a94f3a80a516dd6d3bd4f4ba4bf2af8101caf623 /target/openrisc | |
| parent | 2ba6541792782fc0d20dab6678f5f90a3c8978c9 (diff) | |
target/openrisc: Exit the TB after l.mtspr
A store to SR changes interrupt state, which should return
to the main loop to recognize that state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/translate.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index db149986af..59605aacca 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); + TCGv_i32 ti; + + /* For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } |