diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:02:54 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:48:43 -0700 |
| commit | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 (patch) | |
| tree | 17c8eb391a8d03a3002cee3235df59bce50a7dd5 /target/openrisc/sys_helper.c | |
| parent | b72e3ff65880f2b894a2692e2b0a14424058a919 (diff) | |
target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index d20f48b659..a2b1f52294 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return env->vr; case TO_SPR(0, 1): /* UPR */ - return env->upr; /* TT, DM, IM, UP present */ + return env->upr; case TO_SPR(0, 2): /* CPUCFGR */ return env->cpucfgr; case TO_SPR(0, 3): /* DMMUCFGR */ - return env->dmmucfgr; /* 1Way, 64 entries */ + return env->dmmucfgr; case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; |