diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 19:51:00 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | b9bed1b9ab37a6ae62e88a52cbcbd2ad81aa1056 (patch) | |
| tree | 15dba503a0704eca2b64bf8b77e7621bcd3208b5 /target/openrisc/sys_helper.c | |
| parent | fffde6695f4be3cf484f068f24e894280d7360ea (diff) | |
target/openrisc: Fix cpu_mmu_index
The code in cpu_mmu_index does not properly honor SR_DME.
This bug has workarounds elsewhere in that we flush the
tlb more often than necessary, on the state changes that
should be reflected in a change of mmu_index.
Fixing this means that we can respect the mmu_index that
is given to tlb_flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index c9702cd26c..852b219f9b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -56,10 +56,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(0, 17): /* SR */ - if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ - (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(cs); - } cpu_set_sr(env, rb); break; |