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authorRichard Henderson <rth@twiddle.net>2016-04-05 11:41:48 -0700
committerRichard Henderson <rth@twiddle.net>2017-02-14 08:15:00 +1100
commit24c328521b19aff2559118809ddf0522d6dfaaea (patch)
treed8bd63c5a682fbc3aeb9d019195059928c482477 /target/openrisc/machine.c
parenta8000cb480c8cfb612b039bf0382c41b9d6c7d45 (diff)
target/openrisc: Tidy ppc/npc implementation
The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or attempt to read its contents. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/machine.c')
-rw-r--r--target/openrisc/machine.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 4100957138..686eaa30c9 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -47,12 +47,11 @@ static const VMStateInfo vmstate_sr = {
static const VMStateDescription vmstate_env = {
.name = "env",
- .version_id = 3,
- .minimum_version_id = 3,
+ .version_id = 4,
+ .minimum_version_id = 4,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
- VMSTATE_UINTTL(npc, CPUOpenRISCState),
VMSTATE_UINTTL(ppc, CPUOpenRISCState),
VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),