diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 22:04:46 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | 1cc9e5d896695091eeb126f5c578b02ddd0fc0e4 (patch) | |
| tree | 71efab11d996bde34b4f58531487adb52cc80cdd /target/openrisc/machine.c | |
| parent | 5ce5dad3527e024c297f73f9eb79098235efba6b (diff) | |
target/openrisc: Increase the TLB size
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
- Change VMState version.
Diffstat (limited to 'target/openrisc/machine.c')
| -rw-r--r-- | target/openrisc/machine.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = { static const VMStateDescription vmstate_cpu_tlb = { .name = "cpu_tlb", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), |