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authorRichard Henderson <richard.henderson@linaro.org>2018-05-22 15:02:23 -0700
committerStafford Horne <shorne@gmail.com>2018-07-03 00:05:28 +0900
commit64e46c958162d986cc6e0cdfd6fb8f11b6f31748 (patch)
treec2798555a87354c8c05dde1dc36d885cffca92be /target/openrisc/interrupt_helper.c
parentc86395c850d43047e65892ea41942c18eb29a39d (diff)
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
No need to use the interrupt mechanisms when we can simply exit the tb directly. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/interrupt_helper.c')
-rw-r--r--target/openrisc/interrupt_helper.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index 56620e0571..b865738f8b 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -26,7 +26,6 @@
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
@@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
+ CPUState *cs = CPU(cpu);
tlb_flush(cs);
}
#endif
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}