diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-22 19:51:00 -0700 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-07-03 00:05:28 +0900 |
| commit | b9bed1b9ab37a6ae62e88a52cbcbd2ad81aa1056 (patch) | |
| tree | 15dba503a0704eca2b64bf8b77e7621bcd3208b5 /target/openrisc/interrupt.c | |
| parent | fffde6695f4be3cf484f068f24e894280d7360ea (diff) | |
target/openrisc: Fix cpu_mmu_index
The code in cpu_mmu_index does not properly honor SR_DME.
This bug has workarounds elsewhere in that we flush the
tlb more often than necessary, on the state changes that
should be reflected in a change of mmu_index.
Fixing this means that we can respect the mmu_index that
is given to tlb_flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/interrupt.c')
| -rw-r--r-- | target/openrisc/interrupt.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 23abcf29ed..138ad17f00 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -51,10 +51,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->eear = env->pc; } - /* For machine-state changed between user-mode and supervisor mode, - we need flush TLB when we enter&exit EXCP. */ - tlb_flush(cs); - env->esr = cpu_get_sr(env); env->sr &= ~SR_DME; env->sr &= ~SR_IME; |