diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-20 10:04:14 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-05-14 14:54:24 -0700 |
| commit | 6ad216abfd40a781f202b1f7c61a5fdc4d6710bc (patch) | |
| tree | dd9a788a44ae9dfac6f174934eec4bf6a21b89a5 /target/openrisc/insns.decode | |
| parent | 8816f70b9372f3731d4c0810ab9bdd63b2eafd3b (diff) | |
target/openrisc: Convert dec_calc
Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/insns.decode')
| -rw-r--r-- | target/openrisc/insns.decode | 76 |
1 files changed, 56 insertions, 20 deletions
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 247a2e14f2..20f035f488 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -17,6 +17,10 @@ # License along with this library; if not, see <http://www.gnu.org/licenses/>. # +&dab d a b +&da d a +&ab a b + #### # System Instructions #### @@ -27,7 +31,7 @@ l_msync 001000 1000000000 00000000 00000000 l_psync 001000 1010000000 00000000 00000000 l_csync 001000 1100000000 00000000 00000000 -l_rfe 001001 ----- ----- -------- -------- +l_rfe 001001 ----- ----- -------- -------- #### # Branch Instructions @@ -60,32 +64,64 @@ l_lbs 100100 ..... ..... ........ ........ @load l_lhz 100101 ..... ..... ........ ........ @load l_lhs 100110 ..... ..... ........ ........ @load -l_swa 110011 ..... ..... ..... ........... @store -l_sw 110101 ..... ..... ..... ........... @store -l_sb 110110 ..... ..... ..... ........... @store -l_sh 110111 ..... ..... ..... ........... @store +l_swa 110011 ..... ..... ..... ........... @store +l_sw 110101 ..... ..... ..... ........... @store +l_sb 110110 ..... ..... ..... ........... @store +l_sh 110111 ..... ..... ..... ........... @store #### # Immediate Operand Instructions #### -%mtspr_k 21:5 0:11 +%mtspr_k 21:5 0:11 + +&rri d a i +&rrk d a k +@rri ...... d:5 a:5 i:s16 &rri +@rrk ...... d:5 a:5 k:16 &rrk + +l_nop 000101 01--- ----- k:16 -&rri d a i -&rrk d a k -@rri ...... d:5 a:5 i:s16 &rri -@rrk ...... d:5 a:5 k:16 &rrk +l_addi 100111 ..... ..... ........ ........ @rri +l_addic 101000 ..... ..... ........ ........ @rri +l_andi 101001 ..... ..... ........ ........ @rrk +l_ori 101010 ..... ..... ........ ........ @rrk +l_xori 101011 ..... ..... ........ ........ @rri +l_muli 101100 ..... ..... ........ ........ @rri -l_nop 000101 01--- ----- k:16 +l_mfspr 101101 ..... ..... ........ ........ @rrk +l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k -l_addi 100111 ..... ..... ........ ........ @rri -l_addic 101000 ..... ..... ........ ........ @rri -l_andi 101001 ..... ..... ........ ........ @rrk -l_ori 101010 ..... ..... ........ ........ @rrk -l_xori 101011 ..... ..... ........ ........ @rri -l_muli 101100 ..... ..... ........ ........ @rri +l_maci 010011 ----- a:5 i:s16 -l_mfspr 101101 ..... ..... ........ ........ @rrk -l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k +#### +# Arithmetic Instructions +#### -l_maci 010011 ----- a:5 i:s16 +l_exths 111000 d:5 a:5 ----- - 0000 -- 1100 +l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100 +l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100 +l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100 + +l_add 111000 d:5 a:5 b:5 - 00 ---- 0000 +l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001 +l_sub 111000 d:5 a:5 b:5 - 00 ---- 0010 +l_and 111000 d:5 a:5 b:5 - 00 ---- 0011 +l_or 111000 d:5 a:5 b:5 - 00 ---- 0100 +l_xor 111000 d:5 a:5 b:5 - 00 ---- 0101 +l_cmov 111000 d:5 a:5 b:5 - 00 ---- 1110 +l_ff1 111000 d:5 a:5 ----- - 00 ---- 1111 +l_fl1 111000 d:5 a:5 ----- - 01 ---- 1111 + +l_sll 111000 d:5 a:5 b:5 - 0000 -- 1000 +l_srl 111000 d:5 a:5 b:5 - 0001 -- 1000 +l_sra 111000 d:5 a:5 b:5 - 0010 -- 1000 +l_ror 111000 d:5 a:5 b:5 - 0011 -- 1000 + +l_mul 111000 d:5 a:5 b:5 - 11 ---- 0110 +l_mulu 111000 d:5 a:5 b:5 - 11 ---- 1011 +l_div 111000 d:5 a:5 b:5 - 11 ---- 1001 +l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010 + +l_muld 111000 ----- a:5 b:5 - 11 ---- 0111 +l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100 |