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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:00 +0100 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:16 +0100 |
| commit | 317134bb54bbaf13548c35d92cb00c650a18e32f (patch) | |
| tree | 0b9f925b0bc5b30fa7bd0fc338462c147521c193 /target/openrisc/gdbstub.c | |
| parent | 4f3652b3aa5f77582c94ac434e960db242430eac (diff) | |
| parent | f4d1414a9385e3375d9107b29eeb75d27daf2147 (diff) | |
Merge remote-tracking branch 'shorne/tags/pull-or-20170504' into staging
Openrisc Features and Fixes for qemu 2.10
# gpg: Signature made Thu 04 May 2017 01:41:45 AM BST
# gpg: using RSA key 0xC3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4
* shorne/tags/pull-or-20170504:
target/openrisc: Support non-busy idle state using PMR SPR
target/openrisc: Remove duplicate features property
target/openrisc: Implement full vmstate serialization
migration: Add VMSTATE_STRUCT_2DARRAY()
target/openrisc: implement shadow registers
migration: Add VMSTATE_UINTTL_2DARRAY()
target/openrisc: add numcores and coreid support
target/openrisc: Fixes for memory debugging
target/openrisc: Implement EPH bit
target/openrisc: Implement EVBAR register
MAINTAINERS: Add myself as openrisc maintainer
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/openrisc/gdbstub.c')
| -rw-r--r-- | target/openrisc/gdbstub.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index b18c7e9f05..f9af6507f3 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) CPUOpenRISCState *env = &cpu->env; if (n < 32) { - return gdb_get_reg32(mem_buf, env->gpr[n]); + return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); } else { switch (n) { case 32: /* PPC */ @@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); if (n < 32) { - env->gpr[n] = tmp; + cpu_set_gpr(env, n, tmp); } else { switch (n) { case 32: /* PPC */ |