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authorStafford Horne <shorne@gmail.com>2020-01-11 06:28:43 +0900
committerRichard Henderson <richard.henderson@linaro.org>2020-01-16 14:50:43 -1000
commit97a254b3f03a184136e381c6d9fd80475e1795ac (patch)
tree0e2f6c1cadccbb62d061fd88c1c0313a0cbb454a /target/openrisc/disas.c
parent28b58f19d269633b3d14b6aebf1e92b3cd3ab56e (diff)
target/openrisc: Fix FPCSR mask to allow setting DZF
The mask used when setting FPCSR allows setting bits 10 to 1. However, OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero Flag (DZF). This seems like an off-by-one bug. This was found when testing the GLIBC test suite which has test cases to set and clear all bits. Signed-off-by: Stafford Horne <shorne@gmail.com> Message-Id: <20200110212843.27335-1-shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/disas.c')
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