diff options
| author | Stafford Horne <shorne@gmail.com> | 2017-08-22 06:37:10 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-10-21 06:35:47 +0900 |
| commit | 6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87 (patch) | |
| tree | 9f45d3d741dcb0971bf4be0add6250d9deb0a92d /target/openrisc/cpu.h | |
| parent | 8c949951ed257567303c3d3b83bcd876b53d79e5 (diff) | |
openrisc/cputimer: Perparation for Multicore
In order to support multicore system we move some of the previously
static state variables into the state of each core.
On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec which has a separate timer counter
per core, but it seems the most simple way to keep each clock in sync.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f51b89a11c..892dc4210f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,7 @@ typedef struct CPUOpenRISCState { QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ - uint32_t ttcr; /* Timer tick count register */ + int is_counting; uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ @@ -371,6 +371,8 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); /* hw/openrisc_timer.c */ void cpu_openrisc_clock_init(OpenRISCCPU *cpu); +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); |