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authorRichard Henderson <richard.henderson@linaro.org>2018-05-22 23:14:02 -0700
committerStafford Horne <shorne@gmail.com>2018-07-03 22:40:33 +0900
commitf0655423ca72797fc12763c6a46b69d3eae90a1c (patch)
treeec0691f3c34d7d002fc05b2ae881f58377dff47e /target/openrisc/cpu.h
parent1cc9e5d896695091eeb126f5c578b02ddd0fc0e4 (diff)
target/openrisc: Reorg tlb lookup
While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.h')
-rw-r--r--target/openrisc/cpu.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b180e30e9e..f1b31bc24a 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -237,14 +237,6 @@ enum {
UXE = (1 << 7),
};
-/* check if tlb available */
-enum {
- TLBRET_INVALID = -3,
- TLBRET_NOMATCH = -2,
- TLBRET_BADADDR = -1,
- TLBRET_MATCH = 0
-};
-
typedef struct OpenRISCTLBEntry {
uint32_t mr;
uint32_t tr;