diff options
| author | Richard Henderson <rth@twiddle.net> | 2015-02-18 13:26:26 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-02-14 08:14:59 +1100 |
| commit | 9745807191a81c45970f780166f44a7f93b18653 (patch) | |
| tree | 426a6b0c6b8fe6576c3d564e3bb0672ab794101c /target/openrisc/cpu.h | |
| parent | 84775c43f390d4f5dd9adf8732e7e0b6deed8f61 (diff) | |
target/openrisc: Keep SR_CY and SR_OV in a separate variables
This significantly streamlines carry and overflow production.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bb5d3636f1..e693461118 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -287,7 +287,9 @@ typedef struct CPUOpenRISCState { target_ulong eear; /* Exception EA register */ target_ulong sr_f; /* the SR_F bit, values 0, 1. */ - uint32_t sr; /* Supervisor register, without SR_F */ + target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ + target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ + uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ @@ -414,13 +416,18 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { - return env->sr + env->sr_f * SR_F; + return (env->sr + + env->sr_f * SR_F + + env->sr_cy * SR_CY + + (env->sr_ov < 0) * SR_OV); } static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) { env->sr_f = (val & SR_F) != 0; - env->sr = (val & ~SR_F) | SR_FO; + env->sr_cy = (val & SR_CY) != 0; + env->sr_ov = (val & SR_OV ? -1 : 0); + env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; } #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 |