diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-22 09:19:16 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 08:16:52 -0700 |
| commit | cd419bc63d8f98b07503511286a28cbedab12cd7 (patch) | |
| tree | ba935c30563d20fb8e8d986510c3ade48df95d07 /target/nios2 | |
| parent | 3d1f63d019c7aeaf2d9448ec58eab95c0a1d4a10 (diff) | |
target/nios2: Split out helpers for gen_i_math_logic
Do as little work as possible within the macro.
Split out helper functions and pass in arguments instead.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2')
| -rw-r--r-- | target/nios2/translate.c | 66 |
1 files changed, 43 insertions, 23 deletions
diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 86978ba47a..aa570b6d79 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -83,6 +83,11 @@ static target_ulong imm_signed(const InstrIType *i) return i->imm16.s; } +static target_ulong imm_shifted(const InstrIType *i) +{ + return i->imm16.u << 16; +} + /* R-Type instruction parsing */ typedef struct { uint8_t op; @@ -115,6 +120,8 @@ typedef struct { .imm26 = extract32((code), 6, 26), \ } +typedef void GenFn2i(TCGv, TCGv, target_long); + typedef struct DisasContext { DisasContextBase base; target_ulong pc; @@ -299,29 +306,42 @@ gen_i_cmpxx(gen_cmpxxsi, imm_signed) gen_i_cmpxx(gen_cmpxxui, imm_unsigned) /* Math/logic instructions */ -#define gen_i_math_logic(fname, insn, resimm, op3) \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ -{ \ - I_TYPE(instr, (code)); \ - if (unlikely(instr.b == R_ZERO)) { /* Store to R_ZERO is ignored */ \ - return; \ - } else if (instr.a == R_ZERO) { /* MOVxI optimizations */ \ - tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); \ - } else { \ - tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); \ - } \ -} - -gen_i_math_logic(addi, addi, 1, instr.imm16.s) -gen_i_math_logic(muli, muli, 0, instr.imm16.s) - -gen_i_math_logic(andi, andi, 0, instr.imm16.u) -gen_i_math_logic(ori, ori, 1, instr.imm16.u) -gen_i_math_logic(xori, xori, 1, instr.imm16.u) - -gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16) -gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16) -gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16) +static void do_i_math_logic(DisasContext *dc, uint32_t insn, + GenFn2i *fn, ImmFromIType *imm, + bool x_op_0_eq_x) +{ + I_TYPE(instr, insn); + target_ulong val; + + if (unlikely(instr.b == R_ZERO)) { + /* Store to R_ZERO is ignored -- this catches the canonical NOP. */ + return; + } + + val = imm(&instr); + + if (instr.a == R_ZERO) { + /* This catches the canonical expansions of movi and movhi. */ + tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0); + } else { + fn(cpu_R[instr.b], cpu_R[instr.a], val); + } +} + +#define gen_i_math_logic(fname, insn, x_op_0, imm) \ + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ + { do_i_math_logic(dc, code, tcg_gen_##insn##_tl, imm, x_op_0); } + +gen_i_math_logic(addi, addi, 1, imm_signed) +gen_i_math_logic(muli, muli, 0, imm_signed) + +gen_i_math_logic(andi, andi, 0, imm_unsigned) +gen_i_math_logic(ori, ori, 1, imm_unsigned) +gen_i_math_logic(xori, xori, 1, imm_unsigned) + +gen_i_math_logic(andhi, andi, 0, imm_shifted) +gen_i_math_logic(orhi , ori, 1, imm_shifted) +gen_i_math_logic(xorhi, xori, 1, imm_shifted) /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, |