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authorRichard Henderson <richard.henderson@linaro.org>2022-04-22 09:25:30 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-04-26 08:16:55 -0700
commit7c849046af7cec5efbacdb9b3ff14ebef9abebd6 (patch)
tree214e6d9ab4da068fea5961fde44556e12052fee7 /target/nios2
parentcd419bc63d8f98b07503511286a28cbedab12cd7 (diff)
target/nios2: Split out helpers for gen_r_math_logic
Split the macro in two, one for reg/imm and one for reg/reg. Do as little work as possible within the macros; split out helper functions and pass in arguments instead. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2')
-rw-r--r--target/nios2/translate.c54
1 files changed, 36 insertions, 18 deletions
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index aa570b6d79..4f52606516 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -121,6 +121,7 @@ typedef struct {
}
typedef void GenFn2i(TCGv, TCGv, target_long);
+typedef void GenFn3(TCGv, TCGv, TCGv);
typedef struct DisasContext {
DisasContextBase base;
@@ -628,28 +629,45 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags)
}
/* Math/logic instructions */
-#define gen_r_math_logic(fname, insn, op3) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- R_TYPE(instr, (code)); \
- if (likely(instr.c != R_ZERO)) { \
- tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \
- } \
+static void do_ri_math_logic(DisasContext *dc, uint32_t insn, GenFn2i *fn)
+{
+ R_TYPE(instr, insn);
+
+ if (likely(instr.c != R_ZERO)) {
+ fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5);
+ }
}
-gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(sub, sub_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(mul, mul_tl, load_gpr(dc, instr.b))
+static void do_rr_math_logic(DisasContext *dc, uint32_t insn, GenFn3 *fn)
+{
+ R_TYPE(instr, insn);
+
+ if (likely(instr.c != R_ZERO)) {
+ fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b));
+ }
+}
+
+#define gen_ri_math_logic(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_ri_math_logic(dc, code, tcg_gen_##insn##_tl); }
+
+#define gen_rr_math_logic(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_rr_math_logic(dc, code, tcg_gen_##insn##_tl); }
+
+gen_rr_math_logic(add, add)
+gen_rr_math_logic(sub, sub)
+gen_rr_math_logic(mul, mul)
-gen_r_math_logic(and, and_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(or, or_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(xor, xor_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(nor, nor_tl, load_gpr(dc, instr.b))
+gen_rr_math_logic(and, and)
+gen_rr_math_logic(or, or)
+gen_rr_math_logic(xor, xor)
+gen_rr_math_logic(nor, nor)
-gen_r_math_logic(srai, sari_tl, instr.imm5)
-gen_r_math_logic(srli, shri_tl, instr.imm5)
-gen_r_math_logic(slli, shli_tl, instr.imm5)
-gen_r_math_logic(roli, rotli_tl, instr.imm5)
+gen_ri_math_logic(srai, sari)
+gen_ri_math_logic(srli, shri)
+gen_ri_math_logic(slli, shli)
+gen_ri_math_logic(roli, rotli)
#define gen_r_mul(fname, insn) \
static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \