diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-21 08:17:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 08:16:41 -0700 |
| commit | 2de70d2d967a73c7ae6ad19b69a217da7da98667 (patch) | |
| tree | e07eb4926df54ac7ff63a2c9a3938d5b24b6e419 /target/nios2 | |
| parent | b05550af11763cb96fa5b368cc0cebcb837b7846 (diff) | |
target/nios2: Implement CR_STATUS.RSIE
Without EIC, this bit is RES1. So set the bit at reset,
and add it to the readonly fields of CR_STATUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-40-richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2')
| -rw-r--r-- | target/nios2/cpu.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a0c3e97d72..7d734280d1 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -54,9 +54,9 @@ static void nios2_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->ctrl[CR_STATUS] = 0; + env->ctrl[CR_STATUS] = CR_STATUS_RSIE; #endif } @@ -127,6 +127,7 @@ static void realize_cr_status(CPUState *cs) WR_REG(CR_BADADDR); /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING); |