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authorAmir Gonnen <amir.gonnen@neuroblade.ai>2022-04-21 08:16:46 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-04-26 08:16:41 -0700
commit5ea3e9975b901dc85be3a30931cfa57830f1bd00 (patch)
tree82631083231e7cd5e675c80e572641a58446a802 /target/nios2/cpu.h
parent48b7eac2078f2a85aca094eac10afa1844e5d156 (diff)
target/nios2: Add NUM_GP_REGS and NUM_CP_REGS
Split NUM_CORE_REGS into components that can be used elsewhere. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-16-richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2/cpu.h')
-rw-r--r--target/nios2/cpu.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 3198c17213..09dc38a4e7 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -56,9 +56,11 @@ struct Nios2CPUClass {
#define EXCEPTION_ADDRESS 0x00000004
#define FAST_TLB_MISS_ADDRESS 0x00000008
+#define NUM_GP_REGS 32
+#define NUM_CR_REGS 32
/* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (32 + 32 + 1)
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
/* General purpose register aliases */
#define R_ZERO 0
@@ -79,7 +81,7 @@ struct Nios2CPUClass {
#define R_RA 31
/* Control register aliases */
-#define CR_BASE 32
+#define CR_BASE NUM_GP_REGS
#define CR_STATUS (CR_BASE + 0)
#define CR_STATUS_PIE (1 << 0)
#define CR_STATUS_U (1 << 1)