diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-13 14:46:56 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-07-11 22:29:54 +0200 |
| commit | dce4808f74869577db21ef90a28061f9dc65c5d8 (patch) | |
| tree | 53f1c57a973913b56e7f48a5e4cb0931fefac7fb /target/mips | |
| parent | 71c49f39b9965506fa32483f80980a4a0199d4f8 (diff) | |
target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
Introduce the PROT3W opcode (Parallel Rotate 3 Words).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-25-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tcg/tx79.decode | 1 | ||||
| -rw-r--r-- | target/mips/tcg/tx79_translate.c | 28 |
2 files changed, 29 insertions, 0 deletions
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 653910371d..2f65dce243 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -54,6 +54,7 @@ PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd +PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd # MMI3 diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 90c33d26a9..402790249f 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -593,3 +593,31 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) return true; } + +/* Parallel Rotate 3 Words Left */ +static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax; + + if (a->rd == 0) { + /* nop */ + return true; + } + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ax = tcg_temp_new_i64(); + + tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32); + + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); + tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); + + tcg_temp_free(ax); + + return true; +} |