aboutsummaryrefslogtreecommitdiff
path: root/target/mips
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2023-09-13 16:37:36 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-10-03 08:01:02 -0700
commitad75a51e84af9638e4ec51aa1e6ec5f3ff642558 (patch)
treed6d2af739fb0a9a5dfcd6871a9271eccdf54ab5b /target/mips
parenta953b5fa153fc384d2631cda8213efe983501609 (diff)
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/tcg/lcsr_translate.c6
-rw-r--r--target/mips/tcg/micromips_translate.c.inc12
-rw-r--r--target/mips/tcg/msa_translate.c34
-rw-r--r--target/mips/tcg/mxu_translate.c4
-rw-r--r--target/mips/tcg/nanomips_translate.c.inc200
-rw-r--r--target/mips/tcg/translate.c1284
-rw-r--r--target/mips/tcg/translate.h6
-rw-r--r--target/mips/tcg/vr54xx_translate.c2
8 files changed, 774 insertions, 774 deletions
diff --git a/target/mips/tcg/lcsr_translate.c b/target/mips/tcg/lcsr_translate.c
index 9f2a5f4a37..352b0f4328 100644
--- a/target/mips/tcg/lcsr_translate.c
+++ b/target/mips/tcg/lcsr_translate.c
@@ -22,7 +22,7 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)
TCGv src1 = tcg_temp_new();
gen_load_gpr(src1, a->rs);
- gen_helper_lcsr_cpucfg(dest, cpu_env, src1);
+ gen_helper_lcsr_cpucfg(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd);
return true;
@@ -37,7 +37,7 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a,
check_cp0_enabled(ctx);
gen_load_gpr(src1, a->rs);
- func(dest, cpu_env, src1);
+ func(dest, tcg_env, src1);
gen_store_gpr(dest, a->rd);
return true;
@@ -52,7 +52,7 @@ static bool gen_wrcsr(DisasContext *ctx, arg_r *a,
check_cp0_enabled(ctx);
gen_load_gpr(addr, a->rs);
gen_load_gpr(val, a->rd);
- func(cpu_env, addr, val);
+ func(tcg_env, addr, val);
return true;
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 211d102cf6..7510831701 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -710,17 +710,17 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
save_cpu_state(ctx, 1);
switch (opc) {
case LWM32:
- gen_helper_lwm(cpu_env, t0, t1, t2);
+ gen_helper_lwm(tcg_env, t0, t1, t2);
break;
case SWM32:
- gen_helper_swm(cpu_env, t0, t1, t2);
+ gen_helper_swm(tcg_env, t0, t1, t2);
break;
#ifdef TARGET_MIPS64
case LDM:
- gen_helper_ldm(cpu_env, t0, t1, t2);
+ gen_helper_ldm(tcg_env, t0, t1, t2);
break;
case SDM:
- gen_helper_sdm(cpu_env, t0, t1, t2);
+ gen_helper_sdm(tcg_env, t0, t1, t2);
break;
#endif
}
@@ -1271,7 +1271,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rs);
/*
* Stop translation as we may have switched the execution
@@ -1286,7 +1286,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rs);
/*
* DISAS_STOP isn't sufficient, we need to ensure we break out
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b5b66fb38a..75cf80a20e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -140,7 +140,7 @@ void msa_translate_init(void)
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ tcg_global_mem_new_i64(tcg_env, off, msaregnames[i * 2 + 1]);
}
}
@@ -288,7 +288,7 @@ static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a,
return true;
}
- gen_msa_i8(cpu_env,
+ gen_msa_i8(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->sa));
@@ -314,7 +314,7 @@ static bool trans_SHF(DisasContext *ctx, arg_msa_i *a)
return true;
}
- gen_helper_msa_shf_df(cpu_env,
+ gen_helper_msa_shf_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
@@ -330,7 +330,7 @@ static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a,
return true;
}
- gen_msa_i5(cpu_env,
+ gen_msa_i5(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
@@ -357,7 +357,7 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
return true;
}
- gen_helper_msa_ldi_df(cpu_env,
+ gen_helper_msa_ldi_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->sa));
@@ -376,7 +376,7 @@ static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a,
return true;
}
- gen_msa_bit(cpu_env,
+ gen_msa_bit(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
@@ -405,7 +405,7 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
return true;
}
- gen_msa_3rf(cpu_env,
+ gen_msa_3rf(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
@@ -425,7 +425,7 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
return true;
}
- gen_msa_3r(cpu_env,
+ gen_msa_3r(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->wt));
@@ -519,7 +519,7 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
return true;
}
- gen_helper_msa_move_v(cpu_env,
+ gen_helper_msa_move_v(tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
@@ -537,7 +537,7 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
telm = tcg_temp_new();
gen_load_gpr(telm, a->ws);
- gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));
+ gen_helper_msa_ctcmsa(tcg_env, telm, tcg_constant_i32(a->wd));
return true;
}
@@ -552,7 +552,7 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
telm = tcg_temp_new();
- gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
+ gen_helper_msa_cfcmsa(telm, tcg_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);
return true;
@@ -569,7 +569,7 @@ static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
return true;
}
- gen_msa_elm_df(cpu_env,
+ gen_msa_elm_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
@@ -593,7 +593,7 @@ static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
return true;
}
- gen_msa_elm[a->df](cpu_env,
+ gen_msa_elm[a->df](tcg_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->n));
@@ -698,7 +698,7 @@ static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
return true;
}
- gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
+ gen_msa_2r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
return true;
}
@@ -718,7 +718,7 @@ static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
return true;
}
- gen_helper_msa_fill_df(cpu_env,
+ gen_helper_msa_fill_df(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
@@ -733,7 +733,7 @@ static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
return true;
}
- gen_msa_2rf(cpu_env,
+ gen_msa_2rf(tcg_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws));
@@ -770,7 +770,7 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
taddr = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
- gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);
+ gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);
return true;
}
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index cfcd8ac9bc..c517258ac5 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -617,12 +617,12 @@ static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {
void mxu_translate_init(void)
{
for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
- mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ mxu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
mxuregnames[i]);
}
- mxu_CR = tcg_global_mem_new(cpu_env,
+ mxu_CR = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index d81a7c2d11..b4b746d418 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1006,8 +1006,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
}
gen_store_gpr(tmp1, reg1);
gen_store_gpr(tmp2, reg2);
- tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp));
- tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_i64(tval, tcg_env, offsetof(CPUMIPSState, llval_wp));
+ tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr));
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
@@ -1025,7 +1025,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_ld_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
gen_load_gpr(tmp1, reg1);
@@ -1037,7 +1037,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
}
- tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
+ tcg_gen_ld_i64(llval, tcg_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
eva ? MIPS_HFLAG_UM : ctx->mem_idx,
MO_64 | MO_ALIGN);
@@ -1053,7 +1053,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
}
gen_set_label(lab_done);
tcg_gen_movi_tl(lladdr, -1);
- tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
}
static void gen_adjust_sp(DisasContext *ctx, int u)
@@ -1335,14 +1335,14 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
case NM_DVP:
if (ctx->vp) {
check_cp0_enabled(ctx);
- gen_helper_dvp(t0, cpu_env);
+ gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case NM_EVP:
if (ctx->vp) {
check_cp0_enabled(ctx);
- gen_helper_evp(t0, cpu_env);
+ gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
@@ -1428,7 +1428,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
} else if (rs == 0) {
/* DVPE */
check_cp0_mt(ctx);
- gen_helper_dvpe(t0, cpu_env);
+ gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt);
} else {
gen_reserved_instruction(ctx);
@@ -1443,7 +1443,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
} else if (rs == 0) {
/* EVPE */
check_cp0_mt(ctx);
- gen_helper_evpe(t0, cpu_env);
+ gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt);
} else {
gen_reserved_instruction(ctx);
@@ -1485,7 +1485,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
- gen_helper_yield(t0, cpu_env, t0);
+ gen_helper_yield(t0, tcg_env, t0);
gen_store_gpr(t0, rt);
}
break;
@@ -1517,19 +1517,19 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_MAQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_s_w_phr(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_s_w_phl(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_SA_W_PHR:
check_dsp(ctx);
- gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, tcg_env);
break;
case NM_MAQ_SA_W_PHL:
check_dsp(ctx);
- gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
+ gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1571,11 +1571,11 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP:
tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_mthlip(t0, v0_t, cpu_env);
+ gen_helper_mthlip(t0, v0_t, tcg_env);
break;
case NM_SHILOV:
tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_shilo(t0, v0_t, cpu_env);
+ gen_helper_shilo(t0, v0_t, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1588,24 +1588,24 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 12, 2)) {
case NM_RDDSP:
tcg_gen_movi_tl(t0, imm);
- gen_helper_rddsp(t0, t0, cpu_env);
+ gen_helper_rddsp(t0, t0, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_WRDSP:
gen_load_gpr(t0, ret);
tcg_gen_movi_tl(t1, imm);
- gen_helper_wrdsp(t0, t1, cpu_env);
+ gen_helper_wrdsp(t0, t1, tcg_env);
break;
case NM_EXTP:
tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extp(t0, t0, t1, cpu_env);
+ gen_helper_extp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTPDP:
tcg_gen_movi_tl(t0, v2 >> 3);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extpdp(t0, t0, t1, cpu_env);
+ gen_helper_extpdp(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1615,7 +1615,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_movi_tl(t0, v2 >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case NM_SHLL_QB:
- gen_helper_shll_qb(t0, t0, v0_t, cpu_env);
+ gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_SHRL_QB:
@@ -1634,19 +1634,19 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_gen_movi_tl(t1, v1);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_EXTR_W:
- gen_helper_extr_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_R_W:
- gen_helper_extr_r_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_r_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_RS_W:
- gen_helper_extr_rs_w(t0, t0, t1, cpu_env);
+ gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_S_H:
- gen_helper_extr_s_h(t0, t0, t1, cpu_env);
+ gen_helper_extr_s_h(t0, t0, t1, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1671,19 +1671,19 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPS_W_PH:
check_dsp_r2(ctx);
- gen_helper_dps_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dps_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPSQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1694,19 +1694,19 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpax_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpax_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPAQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env);
+ gen_helper_dpaq_sa_l_w(t0, v0, v1, tcg_env);
break;
case NM_DPSX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPSQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
+ gen_helper_dpsq_sa_l_w(t0, v0, v1, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1717,23 +1717,23 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBL:
check_dsp(ctx);
- gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env);
+ gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env);
break;
case NM_DPAQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpaqx_s_w_ph(t0, v0, v1, tcg_env);
break;
case NM_DPSU_H_QBL:
check_dsp(ctx);
- gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env);
+ gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env);
break;
case NM_DPSQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_dpsqx_s_w_ph(t0, v0, v1, tcg_env);
break;
case NM_MULSA_W_PH:
check_dsp_r2(ctx);
- gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
+ gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1744,23 +1744,23 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAU_H_QBR:
check_dsp(ctx);
- gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env);
+ gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env);
break;
case NM_DPAQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpaqx_sa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_DPSU_H_QBR:
check_dsp(ctx);
- gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env);
+ gen_helper_dpsu_h_qbr(t0, v1, v0, tcg_env);
break;
case NM_DPSQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_dpsqx_sa_w_ph(t0, v1, v0, tcg_env);
break;
case NM_MULSAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
+ gen_helper_mulsaq_s_w_ph(t0, v1, v0, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1849,7 +1849,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
check_dsp(ctx);
gen_load_gpr(v1_t, rs);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1904,7 +1904,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_R_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_r_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
default:
@@ -1924,7 +1924,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTPV:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extp(t0, t0, v1_t, cpu_env);
+ gen_helper_extp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUB:
@@ -1948,7 +1948,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_RS_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1965,7 +1965,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTPDPV:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extpdp(t0, t0, v1_t, cpu_env);
+ gen_helper_extpdp(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUBU:
@@ -1991,7 +1991,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_S_H:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
+ gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -2014,17 +2014,17 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_ABSQ_S_QB:
check_dsp_r2(ctx);
- gen_helper_absq_s_qb(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_qb(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_PH:
check_dsp(ctx);
- gen_helper_absq_s_ph(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_ph(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_W:
check_dsp(ctx);
- gen_helper_absq_s_w(v0_t, v0_t, cpu_env);
+ gen_helper_absq_s_w(v0_t, v0_t, tcg_env);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQ_W_PHL:
@@ -2109,7 +2109,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv tv0 = tcg_temp_new();
gen_load_gpr(tv0, rt);
- gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
+ gen_helper_insv(v0_t, tcg_env, v0_t, tv0);
gen_store_gpr(v0_t, ret);
}
break;
@@ -2243,7 +2243,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -2255,7 +2255,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new();
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -3036,27 +3036,27 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (opc) {
case NM_CMP_EQ_PH:
check_dsp(ctx);
- gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMP_LT_PH:
check_dsp(ctx);
- gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMP_LE_PH:
check_dsp(ctx);
- gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_EQ_QB:
check_dsp(ctx);
- gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_LT_QB:
check_dsp(ctx);
- gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPU_LE_QB:
check_dsp(ctx);
- gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
break;
case NM_CMPGU_EQ_QB:
check_dsp(ctx);
@@ -3098,32 +3098,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_PICK_QB:
check_dsp(ctx);
- gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_pick_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_PICK_PH:
check_dsp(ctx);
- gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_pick_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDQ_S_W:
check_dsp(ctx);
- gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SUBQ_S_W:
check_dsp(ctx);
- gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDSC:
check_dsp(ctx);
- gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addsc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDWC:
check_dsp(ctx);
- gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addwc(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_ADDQ_S_PH:
@@ -3131,12 +3131,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQ_PH */
- gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDQ_S_PH */
- gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3176,12 +3176,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_QB */
- gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDU_S_QB */
- gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3191,12 +3191,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_PH */
- gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* ADDU_S_PH */
- gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3251,12 +3251,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQ_PH */
- gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBQ_S_PH */
- gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3296,12 +3296,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_QB */
- gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBU_S_QB */
- gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3311,12 +3311,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_PH */
- gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SUBU_S_PH */
- gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3341,12 +3341,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SHLLV_PH */
- gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* SHLLV_S_PH */
- gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3376,32 +3376,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_MULEU_S_PH_QBL:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULEU_S_PH_QBR:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_RS_PH:
check_dsp(ctx);
- gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_PH:
check_dsp_r2(ctx);
- gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_RS_W:
check_dsp_r2(ctx);
- gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_W:
check_dsp_r2(ctx);
- gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_APPEND:
@@ -3434,12 +3434,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_SHLLV_QB:
check_dsp(ctx);
- gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_qb(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHLLV_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHILO:
@@ -3451,17 +3451,17 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm);
- gen_helper_shilo(tv0, tv1, cpu_env);
+ gen_helper_shilo(tv0, tv1, tcg_env);
}
break;
case NM_MULEQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULEQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MUL_S_PH:
@@ -3469,12 +3469,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* MUL_PH */
- gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mul_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case 1:
/* MUL_S_PH */
- gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_mul_s_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
}
@@ -3496,12 +3496,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_PRECRQ_RS_PH_W:
check_dsp(ctx);
- gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_PRECRQU_S_QB_PH:
check_dsp(ctx);
- gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, tcg_env);
gen_store_gpr(v1_t, ret);
break;
case NM_SHRA_R_W:
@@ -3532,12 +3532,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
switch (extract32(ctx->opcode, 10, 2)) {
case 0:
/* SHLL_PH */
- gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
case 2:
/* SHLL_S_PH */
- gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_s_ph(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
default:
@@ -3548,7 +3548,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case NM_SHLL_S_W:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd);
- gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env);
+ gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
case NM_REPL_PH:
@@ -4503,7 +4503,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
/* make sure instructions are on a halfword boundary */
if (ctx->base.pc_next & 0x1) {
TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_st_tl(tmp, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
generate_exception_end(ctx, EXCP_AdEL);
return 2;
}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 87e1e0727e..6d5a552b2e 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1268,12 +1268,12 @@ static inline void gen_load_srsgpr(int from, int to)
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
- tcg_gen_add_ptr(addr, cpu_env, addr);
+ tcg_gen_add_ptr(addr, tcg_env, addr);
tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
}
@@ -1288,12 +1288,12 @@ static inline void gen_store_srsgpr(int from, int to)
TCGv_ptr addr = tcg_temp_new_ptr();
gen_load_gpr(t0, from);
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
- tcg_gen_add_ptr(addr, cpu_env, addr);
+ tcg_gen_add_ptr(addr, tcg_env, addr);
tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
}
@@ -1344,14 +1344,14 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
void generate_exception_err(DisasContext *ctx, int excp, int err)
{
save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp),
+ gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp),
tcg_constant_i32(err));
ctx->base.is_jmp = DISAS_NORETURN;
}
void generate_exception(DisasContext *ctx, int excp)
{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+ gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
}
void generate_exception_end(DisasContext *ctx, int excp)
@@ -1363,7 +1363,7 @@ void generate_exception_break(DisasContext *ctx, int code)
{
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
generate_exception_end(ctx, EXCP_BREAK);
@@ -1868,70 +1868,70 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
switch (n) { \
case 0: \
- gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \
break; \
case 1: \
- gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \
break; \
case 2: \
- gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \
break; \
case 3: \
- gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \
break; \
case 4: \
- gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \
break; \
case 5: \
- gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \
break; \
case 6: \
- gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \
break; \
case 7: \
- gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \
break; \
case 8: \
- gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \
break; \
case 9: \
- gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \
break; \
case 10: \
- gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \
break; \
case 11: \
- gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \
break; \
case 12: \
- gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \
break; \
case 13: \
- gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \
break; \
case 14: \
- gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \
break; \
case 15: \
- gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \
break; \
case 17: \
- gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \
break; \
case 18: \
- gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \
break; \
case 19: \
- gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \
break; \
case 25: \
- gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \
break; \
case 26: \
- gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \
break; \
case 27: \
- gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
+ gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \
break; \
default: \
abort(); \
@@ -1954,15 +1954,15 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
- tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); \
+ tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
}
#else
#define OP_LD_ATOMIC(insn, fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
- gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
+ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
OP_LD_ATOMIC(ll, MO_TESL);
@@ -4499,7 +4499,7 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
/* Always trap */
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
generate_exception_end(ctx, EXCP_TRAP);
@@ -4544,7 +4544,7 @@ static void gen_trap(DisasContext *ctx, uint32_t opc,
}
#ifdef CONFIG_USER_ONLY
/* Pass the break code along to cpu_loop. */
- tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
offsetof(CPUMIPSState, error_code));
#endif
/* Like save_cpu_state, only don't update saved values. */
@@ -5053,13 +5053,13 @@ static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(t0, arg);
- tcg_gen_ld_i64(t1, cpu_env, off);
+ tcg_gen_ld_i64(t1, tcg_env, off);
#if defined(TARGET_MIPS64)
tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
#else
tcg_gen_concat32_i64(t1, t1, t0);
#endif
- tcg_gen_st_i64(t1, cpu_env, off);
+ tcg_gen_st_i64(t1, tcg_env, off);
}
static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
@@ -5068,16 +5068,16 @@ static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_ext_tl_i64(t0, arg);
- tcg_gen_ld_i64(t1, cpu_env, off);
+ tcg_gen_ld_i64(t1, tcg_env, off);
tcg_gen_concat32_i64(t1, t1, t0);
- tcg_gen_st_i64(t1, cpu_env, off);
+ tcg_gen_st_i64(t1, tcg_env, off);
}
static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
{
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, off);
+ tcg_gen_ld_i64(t0, tcg_env, off);
#if defined(TARGET_MIPS64)
tcg_gen_shri_i64(t0, t0, 30);
#else
@@ -5090,7 +5090,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
{
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, off);
+ tcg_gen_ld_i64(t0, tcg_env, off);
tcg_gen_shri_i64(t0, t0, 32 + shift);
gen_move_low32(arg, t0);
}
@@ -5099,13 +5099,13 @@ static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, off);
+ tcg_gen_ld_i32(t0, tcg_env, off);
tcg_gen_ext_i32_tl(arg, t0);
}
static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
{
- tcg_gen_ld_tl(arg, cpu_env, off);
+ tcg_gen_ld_tl(arg, tcg_env, off);
tcg_gen_ext32s_tl(arg, arg);
}
@@ -5114,7 +5114,7 @@ static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, arg);
- tcg_gen_st_i32(t0, cpu_env, off);
+ tcg_gen_st_i32(t0, tcg_env, off);
}
#define CP0_CHECK(c) \
@@ -5155,7 +5155,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mfhc0_saar(arg, cpu_env);
+ gen_helper_mfhc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
@@ -5171,7 +5171,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mfhc0_maar(arg, cpu_env);
+ gen_helper_mfhc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
default:
@@ -5256,7 +5256,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mthc0_saar(cpu_env, arg);
+ gen_helper_mthc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
@@ -5276,7 +5276,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mthc0_maar(cpu_env, arg);
+ gen_helper_mthc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
default:
@@ -5353,17 +5353,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg, cpu_env);
+ gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf0(arg, cpu_env);
+ gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf1(arg, cpu_env);
+ gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
case CP0_REG00__VPCONTROL:
@@ -5379,7 +5379,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
- gen_helper_mfc0_random(arg, cpu_env);
+ gen_helper_mfc0_random(arg, tcg_env);
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
@@ -5426,7 +5426,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env,
+ tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
@@ -5441,37 +5441,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcstatus(arg, cpu_env);
+ gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcbind(arg, cpu_env);
+ gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcrestart(arg, cpu_env);
+ gen_helper_mfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tchalt(arg, cpu_env);
+ gen_helper_mfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tccontext(arg, cpu_env);
+ gen_helper_mfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcschedule(arg, cpu_env);
+ gen_helper_mfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcschefback(arg, cpu_env);
+ gen_helper_mfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
default:
@@ -5483,7 +5483,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env,
+ tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
@@ -5508,7 +5508,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
@@ -5519,14 +5519,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
tcg_gen_ext32s_tl(arg, arg);
register_name = "UserLocal";
break;
case CP0_REG04__MMID:
CP0_CHECK(ctx->mi);
- gen_helper_mtc0_memorymapid(cpu_env, arg);
+ gen_helper_mtc0_memorymapid(tcg_env, arg);
register_name = "MMID";
break;
default:
@@ -5546,19 +5546,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
@@ -5635,7 +5635,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_08:
switch (sel) {
case CP0_REG08__BADVADDR:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
@@ -5665,7 +5665,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Mark as an IO operation because we read the time. */
translator_io_start(&ctx->base);
- gen_helper_mfc0_count(arg, cpu_env);
+ gen_helper_mfc0_count(arg, tcg_env);
/*
* Break the TB to be able to take timer interrupts immediately
* after reading count. DISAS_STOP isn't sufficient, we need to
@@ -5682,7 +5682,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mfc0_saar(arg, cpu_env);
+ gen_helper_mfc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
@@ -5692,7 +5692,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
break;
@@ -5749,7 +5749,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
break;
@@ -5765,14 +5765,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "CMGCRBase";
break;
@@ -5822,12 +5822,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mfc0_lladdr(arg, cpu_env);
+ gen_helper_mfc0_lladdr(arg, tcg_env);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mfc0_maar(arg, cpu_env);
+ gen_helper_mfc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
@@ -5880,7 +5880,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
tcg_gen_ext32s_tl(arg, arg);
register_name = "XContext";
break;
@@ -5908,7 +5908,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
register_name = "Debug";
break;
case CP0_REG23__TRACECONTROL:
@@ -5944,7 +5944,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "DEPC";
break;
@@ -6018,7 +6018,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
+ tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo));
gen_move_low32(arg, tmp);
}
register_name = "TagLo";
@@ -6057,7 +6057,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
break;
@@ -6079,7 +6079,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
tcg_gen_ext32s_tl(arg, arg);
register_name = "KScratch";
@@ -6115,12 +6115,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_00:
switch (sel) {
case CP0_REG00__INDEX:
- gen_helper_mtc0_index(cpu_env, arg);
+ gen_helper_mtc0_index(tcg_env, arg);
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_mvpcontrol(cpu_env, arg);
+ gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
@@ -6150,39 +6150,39 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpecontrol(cpu_env, arg);
+ gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf0(cpu_env, arg);
+ gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf1(cpu_env, arg);
+ gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_yqmask(cpu_env, arg);
+ gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeopt(cpu_env, arg);
+ gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
default:
@@ -6192,42 +6192,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- gen_helper_mtc0_entrylo0(cpu_env, arg);
+ gen_helper_mtc0_entrylo0(tcg_env, arg);
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcstatus(cpu_env, arg);
+ gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcbind(cpu_env, arg);
+ gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcrestart(cpu_env, arg);
+ gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tchalt(cpu_env, arg);
+ gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tccontext(cpu_env, arg);
+ gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschedule(cpu_env, arg);
+ gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschefback(cpu_env, arg);
+ gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
default:
@@ -6237,7 +6237,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- gen_helper_mtc0_entrylo1(cpu_env, arg);
+ gen_helper_mtc0_entrylo1(tcg_env, arg);
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
@@ -6252,7 +6252,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- gen_helper_mtc0_context(cpu_env, arg);
+ gen_helper_mtc0_context(tcg_env, arg);
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
@@ -6262,7 +6262,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
@@ -6278,28 +6278,28 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_05:
switch (sel) {
case CP0_REG05__PAGEMASK:
- gen_helper_mtc0_pagemask(cpu_env, arg);
+ gen_helper_mtc0_pagemask(tcg_env, arg);
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_pagegrain(cpu_env, arg);
+ gen_helper_mtc0_pagegrain(tcg_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl0(cpu_env, arg);
+ gen_helper_mtc0_segctl0(tcg_env, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl1(cpu_env, arg);
+ gen_helper_mtc0_segctl1(tcg_env, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl2(cpu_env, arg);
+ gen_helper_mtc0_segctl2(tcg_env, arg);
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
@@ -6309,12 +6309,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- gen_helper_mtc0_pwfield(cpu_env, arg);
+ gen_helper_mtc0_pwfield(tcg_env, arg);
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- gen_helper_mtc0_pwsize(cpu_env, arg);
+ gen_helper_mtc0_pwsize(tcg_env, arg);
register_name = "PWSize";
break;
default:
@@ -6324,37 +6324,37 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_06:
switch (sel) {
case CP0_REG06__WIRED:
- gen_helper_mtc0_wired(cpu_env, arg);
+ gen_helper_mtc0_wired(tcg_env, arg);
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf0(cpu_env, arg);
+ gen_helper_mtc0_srsconf0(tcg_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf1(cpu_env, arg);
+ gen_helper_mtc0_srsconf1(tcg_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf2(cpu_env, arg);
+ gen_helper_mtc0_srsconf2(tcg_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf3(cpu_env, arg);
+ gen_helper_mtc0_srsconf3(tcg_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf4(cpu_env, arg);
+ gen_helper_mtc0_srsconf4(tcg_env, arg);
register_name = "SRSConf4";
break;
case CP0_REG06__PWCTL:
check_pw(ctx);
- gen_helper_mtc0_pwctl(cpu_env, arg);
+ gen_helper_mtc0_pwctl(tcg_env, arg);
register_name = "PWCtl";
break;
default:
@@ -6365,7 +6365,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_hwrena(cpu_env, arg);
+ gen_helper_mtc0_hwrena(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
break;
@@ -6398,17 +6398,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_09:
switch (sel) {
case CP0_REG09__COUNT:
- gen_helper_mtc0_count(cpu_env, arg);
+ gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(cpu_env, arg);
+ gen_helper_mtc0_saari(tcg_env, arg);
register_name = "SAARI";
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(cpu_env, arg);
+ gen_helper_mtc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
@@ -6418,7 +6418,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- gen_helper_mtc0_entryhi(cpu_env, arg);
+ gen_helper_mtc0_entryhi(tcg_env, arg);
register_name = "EntryHi";
break;
default:
@@ -6428,7 +6428,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_11:
switch (sel) {
case CP0_REG11__COMPARE:
- gen_helper_mtc0_compare(cpu_env, arg);
+ gen_helper_mtc0_compare(tcg_env, arg);
register_name = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -6440,7 +6440,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(cpu_env, arg);
+ gen_helper_mtc0_status(tcg_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
@@ -6448,14 +6448,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_intctl(cpu_env, arg);
+ gen_helper_mtc0_intctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsctl(cpu_env, arg);
+ gen_helper_mtc0_srsctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
@@ -6475,7 +6475,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_cause(cpu_env, arg);
+ gen_helper_mtc0_cause(tcg_env, arg);
/*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
@@ -6492,7 +6492,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
@@ -6507,7 +6507,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_ebase(cpu_env, arg);
+ gen_helper_mtc0_ebase(tcg_env, arg);
register_name = "EBase";
break;
default:
@@ -6517,7 +6517,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_16:
switch (sel) {
case CP0_REG16__CONFIG:
- gen_helper_mtc0_config0(cpu_env, arg);
+ gen_helper_mtc0_config0(tcg_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -6527,24 +6527,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Config1";
break;
case CP0_REG16__CONFIG2:
- gen_helper_mtc0_config2(cpu_env, arg);
+ gen_helper_mtc0_config2(tcg_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG3:
- gen_helper_mtc0_config3(cpu_env, arg);
+ gen_helper_mtc0_config3(tcg_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG4:
- gen_helper_mtc0_config4(cpu_env, arg);
+ gen_helper_mtc0_config4(tcg_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG5:
- gen_helper_mtc0_config5(cpu_env, arg);
+ gen_helper_mtc0_config5(tcg_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -6566,17 +6566,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mtc0_lladdr(cpu_env, arg);
+ gen_helper_mtc0_lladdr(tcg_env, arg);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maar(cpu_env, arg);
+ gen_helper_mtc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maari(cpu_env, arg);
+ gen_helper_mtc0_maari(tcg_env, arg);
register_name = "MAARI";
break;
default:
@@ -6624,7 +6624,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(cpu_env, arg);
+ gen_helper_mtc0_xcontext(tcg_env, arg);
register_name = "XContext";
break;
#endif
@@ -6637,7 +6637,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(cpu_env, arg);
+ gen_helper_mtc0_framemask(tcg_env, arg);
register_name = "Framemask";
break;
default:
@@ -6651,7 +6651,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
+ gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
@@ -6659,14 +6659,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -6675,21 +6675,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
/* PDtrace support */
- /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
+ /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceDBPC";
@@ -6702,7 +6702,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
@@ -6712,7 +6712,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_25:
switch (sel) {
case CP0_REG25__PERFCTL0:
- gen_helper_mtc0_performance0(cpu_env, arg);
+ gen_helper_mtc0_performance0(tcg_env, arg);
register_name = "Performance0";
break;
case CP0_REG25__PERFCNT0:
@@ -6750,7 +6750,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_26:
switch (sel) {
case CP0_REG26__ERRCTL:
- gen_helper_mtc0_errctl(cpu_env, arg);
+ gen_helper_mtc0_errctl(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
break;
@@ -6774,14 +6774,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
- gen_helper_mtc0_taglo(cpu_env, arg);
+ gen_helper_mtc0_taglo(tcg_env, arg);
register_name = "TagLo";
break;
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
- gen_helper_mtc0_datalo(cpu_env, arg);
+ gen_helper_mtc0_datalo(tcg_env, arg);
register_name = "DataLo";
break;
default:
@@ -6794,14 +6794,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
- gen_helper_mtc0_taghi(cpu_env, arg);
+ gen_helper_mtc0_taghi(tcg_env, arg);
register_name = "TagHi";
break;
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
- gen_helper_mtc0_datahi(cpu_env, arg);
+ gen_helper_mtc0_datahi(tcg_env, arg);
register_name = "DataHi";
break;
default:
@@ -6812,7 +6812,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
@@ -6833,7 +6833,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
@@ -6880,17 +6880,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpcontrol(arg, cpu_env);
+ gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf0(arg, cpu_env);
+ gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_mvpconf1(arg, cpu_env);
+ gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
case CP0_REG00__VPCONTROL:
@@ -6906,7 +6906,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
- gen_helper_mfc0_random(arg, cpu_env);
+ gen_helper_mfc0_random(arg, tcg_env);
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
@@ -6926,19 +6926,19 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
@@ -6954,43 +6954,43 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcstatus(arg, cpu_env);
+ gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mfc0_tcbind(arg, cpu_env);
+ gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcrestart(arg, cpu_env);
+ gen_helper_dmfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tchalt(arg, cpu_env);
+ gen_helper_dmfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tccontext(arg, cpu_env);
+ gen_helper_dmfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcschedule(arg, cpu_env);
+ gen_helper_dmfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_dmfc0_tcschefback(arg, cpu_env);
+ gen_helper_dmfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
default:
@@ -7000,7 +7000,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
@@ -7015,7 +7015,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
@@ -7025,13 +7025,13 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
case CP0_REG04__MMID:
CP0_CHECK(ctx->mi);
- gen_helper_mtc0_memorymapid(cpu_env, arg);
+ gen_helper_mtc0_memorymapid(tcg_env, arg);
register_name = "MMID";
break;
default:
@@ -7051,32 +7051,32 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
break;
default:
@@ -7137,7 +7137,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_08:
switch (sel) {
case CP0_REG08__BADVADDR:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
case CP0_REG08__BADINSTR:
@@ -7165,7 +7165,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
translator_io_start(&ctx->base);
- gen_helper_mfc0_count(arg, cpu_env);
+ gen_helper_mfc0_count(arg, tcg_env);
/*
* Break the TB to be able to take timer interrupts immediately
* after reading count. DISAS_STOP isn't sufficient, we need to
@@ -7182,7 +7182,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_dmfc0_saar(arg, cpu_env);
+ gen_helper_dmfc0_saar(arg, tcg_env);
register_name = "SAAR";
break;
default:
@@ -7192,7 +7192,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
default:
@@ -7248,7 +7248,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
@@ -7263,13 +7263,13 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase";
break;
default:
@@ -7318,12 +7318,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_dmfc0_lladdr(arg, cpu_env);
+ gen_helper_dmfc0_lladdr(arg, tcg_env);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_dmfc0_maar(arg, cpu_env);
+ gen_helper_dmfc0_maar(arg, tcg_env);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
@@ -7375,7 +7375,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
break;
default:
@@ -7401,32 +7401,32 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
+ gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
register_name = "Debug";
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */
register_name = "TraceControl";
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */
register_name = "TraceControl2";
goto cp0_unimplemented;
case CP0_REG23__USERTRACEDATA1:
/* PDtrace support */
- /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
+ /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/
register_name = "UserTraceData1";
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
+ /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
+ /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */
register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
@@ -7437,7 +7437,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
@@ -7546,7 +7546,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
@@ -7567,7 +7567,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_ld_tl(arg, cpu_env,
+ tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
@@ -7602,12 +7602,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_00:
switch (sel) {
case CP0_REG00__INDEX:
- gen_helper_mtc0_index(cpu_env, arg);
+ gen_helper_mtc0_index(tcg_env, arg);
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_mvpcontrol(cpu_env, arg);
+ gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
@@ -7637,39 +7637,39 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpecontrol(cpu_env, arg);
+ gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf0(cpu_env, arg);
+ gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeconf1(cpu_env, arg);
+ gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_yqmask(cpu_env, arg);
+ gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_vpeopt(cpu_env, arg);
+ gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
default:
@@ -7679,42 +7679,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- gen_helper_dmtc0_entrylo0(cpu_env, arg);
+ gen_helper_dmtc0_entrylo0(tcg_env, arg);
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcstatus(cpu_env, arg);
+ gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcbind(cpu_env, arg);
+ gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcrestart(cpu_env, arg);
+ gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tchalt(cpu_env, arg);
+ gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tccontext(cpu_env, arg);
+ gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschedule(cpu_env, arg);
+ gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- gen_helper_mtc0_tcschefback(cpu_env, arg);
+ gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
default:
@@ -7724,7 +7724,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_03:
switch (sel) {
case CP0_REG03__ENTRYLO1:
- gen_helper_dmtc0_entrylo1(cpu_env, arg);
+ gen_helper_dmtc0_entrylo1(tcg_env, arg);
register_name = "EntryLo1";
break;
case CP0_REG03__GLOBALNUM:
@@ -7739,7 +7739,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_04:
switch (sel) {
case CP0_REG04__CONTEXT:
- gen_helper_mtc0_context(cpu_env, arg);
+ gen_helper_mtc0_context(tcg_env, arg);
register_name = "Context";
break;
case CP0_REG04__CONTEXTCONFIG:
@@ -7749,7 +7749,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
register_name = "UserLocal";
break;
@@ -7765,42 +7765,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_05:
switch (sel) {
case CP0_REG05__PAGEMASK:
- gen_helper_mtc0_pagemask(cpu_env, arg);
+ gen_helper_mtc0_pagemask(tcg_env, arg);
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_pagegrain(cpu_env, arg);
+ gen_helper_mtc0_pagegrain(tcg_env, arg);
register_name = "PageGrain";
break;
case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl0(cpu_env, arg);
+ gen_helper_mtc0_segctl0(tcg_env, arg);
register_name = "SegCtl0";
break;
case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl1(cpu_env, arg);
+ gen_helper_mtc0_segctl1(tcg_env, arg);
register_name = "SegCtl1";
break;
case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
- gen_helper_mtc0_segctl2(cpu_env, arg);
+ gen_helper_mtc0_segctl2(tcg_env, arg);
register_name = "SegCtl2";
break;
case CP0_REG05__PWBASE:
check_pw(ctx);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
case CP0_REG05__PWFIELD:
check_pw(ctx);
- gen_helper_mtc0_pwfield(cpu_env, arg);
+ gen_helper_mtc0_pwfield(tcg_env, arg);
register_name = "PWField";
break;
case CP0_REG05__PWSIZE:
check_pw(ctx);
- gen_helper_mtc0_pwsize(cpu_env, arg);
+ gen_helper_mtc0_pwsize(tcg_env, arg);
register_name = "PWSize";
break;
default:
@@ -7810,37 +7810,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_06:
switch (sel) {
case CP0_REG06__WIRED:
- gen_helper_mtc0_wired(cpu_env, arg);
+ gen_helper_mtc0_wired(tcg_env, arg);
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf0(cpu_env, arg);
+ gen_helper_mtc0_srsconf0(tcg_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf1(cpu_env, arg);
+ gen_helper_mtc0_srsconf1(tcg_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf2(cpu_env, arg);
+ gen_helper_mtc0_srsconf2(tcg_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf3(cpu_env, arg);
+ gen_helper_mtc0_srsconf3(tcg_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsconf4(cpu_env, arg);
+ gen_helper_mtc0_srsconf4(tcg_env, arg);
register_name = "SRSConf4";
break;
case CP0_REG06__PWCTL:
check_pw(ctx);
- gen_helper_mtc0_pwctl(cpu_env, arg);
+ gen_helper_mtc0_pwctl(tcg_env, arg);
register_name = "PWCtl";
break;
default:
@@ -7851,7 +7851,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_hwrena(cpu_env, arg);
+ gen_helper_mtc0_hwrena(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
break;
@@ -7884,17 +7884,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_09:
switch (sel) {
case CP0_REG09__COUNT:
- gen_helper_mtc0_count(cpu_env, arg);
+ gen_helper_mtc0_count(tcg_env, arg);
register_name = "Count";
break;
case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saari(cpu_env, arg);
+ gen_helper_mtc0_saari(tcg_env, arg);
register_name = "SAARI";
break;
case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
- gen_helper_mtc0_saar(cpu_env, arg);
+ gen_helper_mtc0_saar(tcg_env, arg);
register_name = "SAAR";
break;
default:
@@ -7906,7 +7906,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_10:
switch (sel) {
case CP0_REG10__ENTRYHI:
- gen_helper_mtc0_entryhi(cpu_env, arg);
+ gen_helper_mtc0_entryhi(tcg_env, arg);
register_name = "EntryHi";
break;
default:
@@ -7916,7 +7916,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_11:
switch (sel) {
case CP0_REG11__COMPARE:
- gen_helper_mtc0_compare(cpu_env, arg);
+ gen_helper_mtc0_compare(tcg_env, arg);
register_name = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -7930,7 +7930,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_status(cpu_env, arg);
+ gen_helper_mtc0_status(tcg_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
@@ -7938,14 +7938,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_intctl(cpu_env, arg);
+ gen_helper_mtc0_intctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_srsctl(cpu_env, arg);
+ gen_helper_mtc0_srsctl(tcg_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
@@ -7965,7 +7965,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
- gen_helper_mtc0_cause(cpu_env, arg);
+ gen_helper_mtc0_cause(tcg_env, arg);
/*
* Stop translation as we may have triggered an interrupt.
* DISAS_STOP isn't sufficient, we need to ensure we break out of
@@ -7982,7 +7982,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_14:
switch (sel) {
case CP0_REG14__EPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
default:
@@ -7997,7 +7997,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS_R2);
- gen_helper_mtc0_ebase(cpu_env, arg);
+ gen_helper_mtc0_ebase(tcg_env, arg);
register_name = "EBase";
break;
default:
@@ -8007,7 +8007,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_16:
switch (sel) {
case CP0_REG16__CONFIG:
- gen_helper_mtc0_config0(cpu_env, arg);
+ gen_helper_mtc0_config0(tcg_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8017,13 +8017,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Config1";
break;
case CP0_REG16__CONFIG2:
- gen_helper_mtc0_config2(cpu_env, arg);
+ gen_helper_mtc0_config2(tcg_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case CP0_REG16__CONFIG3:
- gen_helper_mtc0_config3(cpu_env, arg);
+ gen_helper_mtc0_config3(tcg_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8033,7 +8033,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Config4";
break;
case CP0_REG16__CONFIG5:
- gen_helper_mtc0_config5(cpu_env, arg);
+ gen_helper_mtc0_config5(tcg_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8047,17 +8047,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_17:
switch (sel) {
case CP0_REG17__LLADDR:
- gen_helper_mtc0_lladdr(cpu_env, arg);
+ gen_helper_mtc0_lladdr(tcg_env, arg);
register_name = "LLAddr";
break;
case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maar(cpu_env, arg);
+ gen_helper_mtc0_maar(tcg_env, arg);
register_name = "MAAR";
break;
case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
- gen_helper_mtc0_maari(cpu_env, arg);
+ gen_helper_mtc0_maari(tcg_env, arg);
register_name = "MAARI";
break;
default:
@@ -8104,7 +8104,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(cpu_env, arg);
+ gen_helper_mtc0_xcontext(tcg_env, arg);
register_name = "XContext";
break;
default:
@@ -8116,7 +8116,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(cpu_env, arg);
+ gen_helper_mtc0_framemask(tcg_env, arg);
register_name = "Framemask";
break;
default:
@@ -8130,7 +8130,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_23:
switch (sel) {
case CP0_REG23__DEBUG:
- gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
+ gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
@@ -8138,35 +8138,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG23__TRACECONTROL:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl";
goto cp0_unimplemented;
case CP0_REG23__TRACECONTROL2:
/* PDtrace support */
- /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
+ /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl2";
goto cp0_unimplemented;
case CP0_REG23__USERTRACEDATA1:
/* PDtrace support */
- /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
+ /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "UserTraceData1";
goto cp0_unimplemented;
case CP0_REG23__TRACEIBPC:
/* PDtrace support */
- /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceIBPC";
goto cp0_unimplemented;
case CP0_REG23__TRACEDBPC:
/* PDtrace support */
- /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceDBPC";
@@ -8179,7 +8179,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) {
case CP0_REG24__DEPC:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
break;
default:
@@ -8189,35 +8189,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_25:
switch (sel) {
case CP0_REG25__PERFCTL0:
- gen_helper_mtc0_performance0(cpu_env, arg);
+ gen_helper_mtc0_performance0(tcg_env, arg);
register_name = "Performance0";
break;
case CP0_REG25__PERFCNT0:
- /* gen_helper_mtc0_performance1(cpu_env, arg); */
+ /* gen_helper_mtc0_performance1(tcg_env, arg); */
register_name = "Performance1";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL1:
- /* gen_helper_mtc0_performance2(cpu_env, arg); */
+ /* gen_helper_mtc0_performance2(tcg_env, arg); */
register_name = "Performance2";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT1:
- /* gen_helper_mtc0_performance3(cpu_env, arg); */
+ /* gen_helper_mtc0_performance3(tcg_env, arg); */
register_name = "Performance3";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL2:
- /* gen_helper_mtc0_performance4(cpu_env, arg); */
+ /* gen_helper_mtc0_performance4(tcg_env, arg); */
register_name = "Performance4";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT2:
- /* gen_helper_mtc0_performance5(cpu_env, arg); */
+ /* gen_helper_mtc0_performance5(tcg_env, arg); */
register_name = "Performance5";
goto cp0_unimplemented;
case CP0_REG25__PERFCTL3:
- /* gen_helper_mtc0_performance6(cpu_env, arg); */
+ /* gen_helper_mtc0_performance6(tcg_env, arg); */
register_name = "Performance6";
goto cp0_unimplemented;
case CP0_REG25__PERFCNT3:
- /* gen_helper_mtc0_performance7(cpu_env, arg); */
+ /* gen_helper_mtc0_performance7(tcg_env, arg); */
register_name = "Performance7";
goto cp0_unimplemented;
default:
@@ -8227,7 +8227,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_26:
switch (sel) {
case CP0_REG26__ERRCTL:
- gen_helper_mtc0_errctl(cpu_env, arg);
+ gen_helper_mtc0_errctl(tcg_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
break;
@@ -8251,14 +8251,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
- gen_helper_mtc0_taglo(cpu_env, arg);
+ gen_helper_mtc0_taglo(tcg_env, arg);
register_name = "TagLo";
break;
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
- gen_helper_mtc0_datalo(cpu_env, arg);
+ gen_helper_mtc0_datalo(tcg_env, arg);
register_name = "DataLo";
break;
default:
@@ -8271,14 +8271,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG29__TAGHI1:
case CP0_REG29__TAGHI2:
case CP0_REG29__TAGHI3:
- gen_helper_mtc0_taghi(cpu_env, arg);
+ gen_helper_mtc0_taghi(tcg_env, arg);
register_name = "TagHi";
break;
case CP0_REG29__DATAHI:
case CP0_REG29__DATAHI1:
case CP0_REG29__DATAHI2:
case CP0_REG29__DATAHI3:
- gen_helper_mtc0_datahi(cpu_env, arg);
+ gen_helper_mtc0_datahi(tcg_env, arg);
register_name = "DataHi";
break;
default:
@@ -8289,7 +8289,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_30:
switch (sel) {
case CP0_REG30__ERROREPC:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
default:
@@ -8310,7 +8310,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH5:
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
- tcg_gen_st_tl(arg, cpu_env,
+ tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
@@ -8358,10 +8358,10 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 1:
switch (sel) {
case 1:
- gen_helper_mftc0_vpecontrol(t0, cpu_env);
+ gen_helper_mftc0_vpecontrol(t0, tcg_env);
break;
case 2:
- gen_helper_mftc0_vpeconf0(t0, cpu_env);
+ gen_helper_mftc0_vpeconf0(t0, tcg_env);
break;
default:
goto die;
@@ -8371,25 +8371,25 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 2:
switch (sel) {
case 1:
- gen_helper_mftc0_tcstatus(t0, cpu_env);
+ gen_helper_mftc0_tcstatus(t0, tcg_env);
break;
case 2:
- gen_helper_mftc0_tcbind(t0, cpu_env);
+ gen_helper_mftc0_tcbind(t0, tcg_env);
break;
case 3:
- gen_helper_mftc0_tcrestart(t0, cpu_env);
+ gen_helper_mftc0_tcrestart(t0, tcg_env);
break;
case 4:
- gen_helper_mftc0_tchalt(t0, cpu_env);
+ gen_helper_mftc0_tchalt(t0, tcg_env);
break;
case 5:
- gen_helper_mftc0_tccontext(t0, cpu_env);
+ gen_helper_mftc0_tccontext(t0, tcg_env);
break;
case 6:
- gen_helper_mftc0_tcschedule(t0, cpu_env);
+ gen_helper_mftc0_tcschedule(t0, tcg_env);
break;
case 7:
- gen_helper_mftc0_tcschefback(t0, cpu_env);
+ gen_helper_mftc0_tcschefback(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
@@ -8399,7 +8399,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 10:
switch (sel) {
case 0:
- gen_helper_mftc0_entryhi(t0, cpu_env);
+ gen_helper_mftc0_entryhi(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
@@ -8409,7 +8409,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 12:
switch (sel) {
case 0:
- gen_helper_mftc0_status(t0, cpu_env);
+ gen_helper_mftc0_status(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
@@ -8419,7 +8419,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 13:
switch (sel) {
case 0:
- gen_helper_mftc0_cause(t0, cpu_env);
+ gen_helper_mftc0_cause(t0, tcg_env);
break;
default:
goto die;
@@ -8429,7 +8429,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 14:
switch (sel) {
case 0:
- gen_helper_mftc0_epc(t0, cpu_env);
+ gen_helper_mftc0_epc(t0, tcg_env);
break;
default:
goto die;
@@ -8439,7 +8439,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 15:
switch (sel) {
case 1:
- gen_helper_mftc0_ebase(t0, cpu_env);
+ gen_helper_mftc0_ebase(t0, tcg_env);
break;
default:
goto die;
@@ -8456,7 +8456,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 5:
case 6:
case 7:
- gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel));
+ gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel));
break;
default:
goto die;
@@ -8466,7 +8466,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
case 23:
switch (sel) {
case 0:
- gen_helper_mftc0_debug(t0, cpu_env);
+ gen_helper_mftc0_debug(t0, tcg_env);
break;
default:
gen_mfc0(ctx, t0, rt, sel);
@@ -8522,7 +8522,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
gen_helper_1e0i(mftacx, t0, 3);
break;
case 16:
- gen_helper_mftdsp(t0, cpu_env);
+ gen_helper_mftdsp(t0, tcg_env);
break;
default:
goto die;
@@ -8585,10 +8585,10 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 1:
switch (sel) {
case 1:
- gen_helper_mttc0_vpecontrol(cpu_env, t0);
+ gen_helper_mttc0_vpecontrol(tcg_env, t0);
break;
case 2:
- gen_helper_mttc0_vpeconf0(cpu_env, t0);
+ gen_helper_mttc0_vpeconf0(tcg_env, t0);
break;
default:
goto die;
@@ -8598,25 +8598,25 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 2:
switch (sel) {
case 1:
- gen_helper_mttc0_tcstatus(cpu_env, t0);
+ gen_helper_mttc0_tcstatus(tcg_env, t0);
break;
case 2:
- gen_helper_mttc0_tcbind(cpu_env, t0);
+ gen_helper_mttc0_tcbind(tcg_env, t0);
break;
case 3:
- gen_helper_mttc0_tcrestart(cpu_env, t0);
+ gen_helper_mttc0_tcrestart(tcg_env, t0);
break;
case 4:
- gen_helper_mttc0_tchalt(cpu_env, t0);
+ gen_helper_mttc0_tchalt(tcg_env, t0);
break;
case 5:
- gen_helper_mttc0_tccontext(cpu_env, t0);
+ gen_helper_mttc0_tccontext(tcg_env, t0);
break;
case 6:
- gen_helper_mttc0_tcschedule(cpu_env, t0);
+ gen_helper_mttc0_tcschedule(tcg_env, t0);
break;
case 7:
- gen_helper_mttc0_tcschefback(cpu_env, t0);
+ gen_helper_mttc0_tcschefback(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
@@ -8626,7 +8626,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 10:
switch (sel) {
case 0:
- gen_helper_mttc0_entryhi(cpu_env, t0);
+ gen_helper_mttc0_entryhi(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
@@ -8636,7 +8636,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 12:
switch (sel) {
case 0:
- gen_helper_mttc0_status(cpu_env, t0);
+ gen_helper_mttc0_status(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
@@ -8646,7 +8646,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 13:
switch (sel) {
case 0:
- gen_helper_mttc0_cause(cpu_env, t0);
+ gen_helper_mttc0_cause(tcg_env, t0);
break;
default:
goto die;
@@ -8656,7 +8656,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 15:
switch (sel) {
case 1:
- gen_helper_mttc0_ebase(cpu_env, t0);
+ gen_helper_mttc0_ebase(tcg_env, t0);
break;
default:
goto die;
@@ -8666,7 +8666,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
case 23:
switch (sel) {
case 0:
- gen_helper_mttc0_debug(cpu_env, t0);
+ gen_helper_mttc0_debug(tcg_env, t0);
break;
default:
gen_mtc0(ctx, t0, rd, sel);
@@ -8722,7 +8722,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
gen_helper_0e1i(mttacx, t0, 3);
break;
case 16:
- gen_helper_mttdsp(cpu_env, t0);
+ gen_helper_mttdsp(tcg_env, t0);
break;
default:
goto die;
@@ -8849,7 +8849,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (!env->tlb->helper_tlbwi) {
goto die;
}
- gen_helper_tlbwi(cpu_env);
+ gen_helper_tlbwi(tcg_env);
break;
case OPC_TLBINV:
opn = "tlbinv";
@@ -8857,7 +8857,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (!env->tlb->helper_tlbinv) {
goto die;
}
- gen_helper_tlbinv(cpu_env);
+ gen_helper_tlbinv(tcg_env);
} /* treat as nop if TLBINV not supported */
break;
case OPC_TLBINVF:
@@ -8866,7 +8866,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (!env->tlb->helper_tlbinvf) {
goto die;
}
- gen_helper_tlbinvf(cpu_env);
+ gen_helper_tlbinvf(tcg_env);
} /* treat as nop if TLBINV not supported */
break;
case OPC_TLBWR:
@@ -8874,21 +8874,21 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
if (!env->tlb->helper_tlbwr) {
goto die;
}
- gen_helper_tlbwr(cpu_env);
+ gen_helper_tlbwr(tcg_env);
break;
case OPC_TLBP:
opn = "tlbp";
if (!env->tlb->helper_tlbp) {
goto die;
}
- gen_helper_tlbp(cpu_env);
+ gen_helper_tlbp(tcg_env);
break;
case OPC_TLBR:
opn = "tlbr";
if (!env->tlb->helper_tlbr) {
goto die;
}
- gen_helper_tlbr(cpu_env);
+ gen_helper_tlbr(tcg_env);
break;
case OPC_ERET: /* OPC_ERETNC */
if ((ctx->insn_flags & ISA_MIPS_R6) &&
@@ -8900,12 +8900,12 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
/* OPC_ERETNC */
opn = "eretnc";
check_insn(ctx, ISA_MIPS_R5);
- gen_helper_eretnc(cpu_env);
+ gen_helper_eretnc(tcg_env);
} else {
/* OPC_ERET */
opn = "eret";
check_insn(ctx, ISA_MIPS2);
- gen_helper_eret(cpu_env);
+ gen_helper_eret(tcg_env);
}
ctx->base.is_jmp = DISAS_EXIT;
}
@@ -8921,7 +8921,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
MIPS_INVAL(opn);
gen_reserved_instruction(ctx);
} else {
- gen_helper_deret(cpu_env);
+ gen_helper_deret(tcg_env);
ctx->base.is_jmp = DISAS_EXIT;
}
break;
@@ -8936,7 +8936,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
ctx->base.pc_next += 4;
save_cpu_state(ctx, 1);
ctx->base.pc_next -= 4;
- gen_helper_wait(cpu_env);
+ gen_helper_wait(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
@@ -9557,7 +9557,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9568,7 +9568,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9579,7 +9579,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9590,7 +9590,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_div_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9599,7 +9599,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
+ gen_helper_float_sqrt_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9645,9 +9645,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_round_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_round_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
@@ -9660,9 +9660,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_trunc_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
@@ -9675,9 +9675,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_ceil_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
@@ -9690,9 +9690,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_floor_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
@@ -9703,9 +9703,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_round_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_round_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
@@ -9716,9 +9716,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
@@ -9729,9 +9729,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
@@ -9742,9 +9742,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_floor_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
@@ -9800,7 +9800,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_recip_s(fp0, cpu_env, fp0);
+ gen_helper_float_recip_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9809,7 +9809,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9822,7 +9822,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fd);
- gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -9835,7 +9835,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fd);
- gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -9844,7 +9844,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rint_s(fp0, cpu_env, fp0);
+ gen_helper_float_rint_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9853,7 +9853,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_class_s(fp0, cpu_env, fp0);
+ gen_helper_float_class_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -9865,7 +9865,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
+ gen_helper_float_min_s(fp2, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
} else {
/* OPC_RECIP2_S */
@@ -9876,7 +9876,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
}
@@ -9889,7 +9889,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp2 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
+ gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp2, fd);
} else {
/* OPC_RECIP1_S */
@@ -9898,7 +9898,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_recip1_s(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
}
@@ -9910,7 +9910,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_max_s(fp1, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
} else {
/* OPC_RSQRT1_S */
@@ -9919,7 +9919,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
}
@@ -9931,7 +9931,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp1 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp1, fd);
} else {
/* OPC_RSQRT2_S */
@@ -9942,7 +9942,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
- gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1);
gen_store_fpr32(ctx, fp0, fd);
}
}
@@ -9954,7 +9954,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvtd_s(fp64, tcg_env, fp32);
gen_store_fpr64(ctx, fp64, fd);
}
break;
@@ -9964,9 +9964,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0);
} else {
- gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_w_s(fp0, tcg_env, fp0);
}
gen_store_fpr32(ctx, fp0, fd);
}
@@ -9979,9 +9979,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr32(ctx, fp32, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32);
} else {
- gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
+ gen_helper_float_cvt_l_s(fp64, tcg_env, fp32);
}
gen_store_fpr64(ctx, fp64, fd);
}
@@ -10030,7 +10030,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10042,7 +10042,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10054,7 +10054,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10066,7 +10066,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_div_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10076,7 +10076,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
+ gen_helper_float_sqrt_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10124,9 +10124,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_round_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_round_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
@@ -10138,9 +10138,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_trunc_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
@@ -10152,9 +10152,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_ceil_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
@@ -10166,9 +10166,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_floor_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
@@ -10181,9 +10181,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_round_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_round_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
@@ -10196,9 +10196,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_trunc_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
@@ -10211,9 +10211,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_ceil_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
@@ -10226,9 +10226,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_floor_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
@@ -10285,7 +10285,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip_d(fp0, cpu_env, fp0);
+ gen_helper_float_recip_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10295,7 +10295,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10308,7 +10308,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fd);
- gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -10321,7 +10321,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fd);
- gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -10330,7 +10330,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rint_d(fp0, cpu_env, fp0);
+ gen_helper_float_rint_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10339,7 +10339,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_class_d(fp0, cpu_env, fp0);
+ gen_helper_float_class_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10350,7 +10350,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_min_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RECIP2_D */
@@ -10361,7 +10361,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
}
@@ -10373,7 +10373,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RECIP1_D */
@@ -10382,7 +10382,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_d(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
}
@@ -10394,7 +10394,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_max_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RSQRT1_D */
@@ -10403,7 +10403,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
}
@@ -10415,7 +10415,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
+ gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp1, fd);
} else {
/* OPC_RSQRT2_D */
@@ -10426,7 +10426,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
}
@@ -10461,7 +10461,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvts_d(fp32, tcg_env, fp64);
gen_store_fpr32(ctx, fp32, fd);
}
break;
@@ -10473,9 +10473,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp64, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64);
} else {
- gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
+ gen_helper_float_cvt_w_d(fp32, tcg_env, fp64);
}
gen_store_fpr32(ctx, fp32, fd);
}
@@ -10487,9 +10487,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
if (ctx->nan2008) {
- gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0);
} else {
- gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
+ gen_helper_float_cvt_l_d(fp0, tcg_env, fp0);
}
gen_store_fpr64(ctx, fp0, fd);
}
@@ -10499,7 +10499,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_cvts_w(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_w(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -10510,7 +10510,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr32(ctx, fp32, fs);
- gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
+ gen_helper_float_cvtd_w(fp64, tcg_env, fp32);
gen_store_fpr64(ctx, fp64, fd);
}
break;
@@ -10521,7 +10521,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp64 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp64, fs);
- gen_helper_float_cvts_l(fp32, cpu_env, fp64);
+ gen_helper_float_cvts_l(fp32, tcg_env, fp64);
gen_store_fpr32(ctx, fp32, fd);
}
break;
@@ -10531,7 +10531,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
+ gen_helper_float_cvtd_l(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10541,7 +10541,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
+ gen_helper_float_cvtps_pw(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10553,7 +10553,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10565,7 +10565,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10577,7 +10577,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10652,7 +10652,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10664,7 +10664,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, ft);
gen_load_fpr64(ctx, fp1, fs);
- gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10676,7 +10676,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10686,7 +10686,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
+ gen_helper_float_recip1_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10696,7 +10696,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
+ gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10708,7 +10708,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
- gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
+ gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10718,7 +10718,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32h(ctx, fp0, fs);
- gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_pu(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -10728,7 +10728,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
+ gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10738,7 +10738,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
+ gen_helper_float_cvts_pl(fp0, tcg_env, fp0);
gen_store_fpr32(ctx, fp0, fd);
}
break;
@@ -10943,7 +10943,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -10958,7 +10958,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -10972,7 +10972,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -10986,7 +10986,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -11001,7 +11001,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11015,7 +11015,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11029,7 +11029,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -11044,7 +11044,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11058,7 +11058,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11072,7 +11072,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr32(ctx, fp0, fs);
gen_load_fpr32(ctx, fp1, ft);
gen_load_fpr32(ctx, fp2, fr);
- gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr32(ctx, fp2, fd);
}
break;
@@ -11087,7 +11087,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11101,7 +11101,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, ft);
gen_load_fpr64(ctx, fp2, fr);
- gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
+ gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2);
gen_store_fpr64(ctx, fp2, fd);
}
break;
@@ -11127,16 +11127,16 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
switch (rd) {
case 0:
- gen_helper_rdhwr_cpunum(t0, cpu_env);
+ gen_helper_rdhwr_cpunum(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 1:
- gen_helper_rdhwr_synci_step(t0, cpu_env);
+ gen_helper_rdhwr_synci_step(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 2:
translator_io_start(&ctx->base);
- gen_helper_rdhwr_cc(t0, cpu_env);
+ gen_helper_rdhwr_cc(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* Break the TB to be able to take timer interrupts immediately
@@ -11147,7 +11147,7 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
ctx->base.is_jmp = DISAS_EXIT;
break;
case 3:
- gen_helper_rdhwr_ccres(t0, cpu_env);
+ gen_helper_rdhwr_ccres(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 4:
@@ -11159,24 +11159,24 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
*/
generate_exception(ctx, EXCP_RI);
}
- gen_helper_rdhwr_performance(t0, cpu_env);
+ gen_helper_rdhwr_performance(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 5:
check_insn(ctx, ISA_MIPS_R6);
- gen_helper_rdhwr_xnp(t0, cpu_env);
+ gen_helper_rdhwr_xnp(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case 29:
#if defined(CONFIG_USER_ONLY)
- tcg_gen_ld_tl(t0, cpu_env,
+ tcg_gen_ld_tl(t0, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
break;
#else
if ((ctx->hflags & MIPS_HFLAG_CP0) ||
(ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
- tcg_gen_ld_tl(t0, cpu_env,
+ tcg_gen_ld_tl(t0, tcg_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
} else {
@@ -11513,7 +11513,7 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
TCGv_i32 t0 = tcg_constant_i32(op);
TCGv t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t1, base, offset);
- gen_helper_cache(cpu_env, t1, t0);
+ gen_helper_cache(tcg_env, t1, t0);
}
static inline bool is_uhi(DisasContext *ctx, int sdbbp_code)
@@ -11710,15 +11710,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_ABSQ_S_QB:
check_dsp_r2(ctx);
- gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_PH:
check_dsp(ctx);
- gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_W:
check_dsp(ctx);
- gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_PRECEQ_W_PHL:
check_dsp(ctx);
@@ -11769,67 +11769,67 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_ADDQ_PH:
check_dsp(ctx);
- gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_PH:
check_dsp(ctx);
- gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_W:
check_dsp(ctx);
- gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_QB:
check_dsp(ctx);
- gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_QB:
check_dsp(ctx);
- gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_PH:
check_dsp_r2(ctx);
- gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_PH:
check_dsp_r2(ctx);
- gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_PH:
check_dsp(ctx);
- gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_PH:
check_dsp(ctx);
- gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_W:
check_dsp(ctx);
- gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_QB:
check_dsp(ctx);
- gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_QB:
check_dsp(ctx);
- gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_PH:
check_dsp_r2(ctx);
- gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_PH:
check_dsp_r2(ctx);
- gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDSC:
check_dsp(ctx);
- gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDWC:
check_dsp(ctx);
- gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MODSUB:
check_dsp(ctx);
@@ -11873,11 +11873,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_PRECRQ_RS_PH_W:
check_dsp(ctx);
- gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PRECRQU_S_QB_PH:
check_dsp(ctx);
- gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -11942,15 +11942,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_ABSQ_S_OB:
check_dsp_r2(ctx);
- gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_PW:
check_dsp(ctx);
- gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env);
break;
case OPC_ABSQ_S_QH:
check_dsp(ctx);
- gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
+ gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env);
break;
}
break;
@@ -11962,35 +11962,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_SUBQ_PW:
check_dsp(ctx);
- gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_PW:
check_dsp(ctx);
- gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_QH:
check_dsp(ctx);
- gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBQ_S_QH:
check_dsp(ctx);
- gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_OB:
check_dsp(ctx);
- gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_OB:
check_dsp(ctx);
- gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_QH:
check_dsp_r2(ctx);
- gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBU_S_QH:
check_dsp_r2(ctx);
- gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SUBUH_OB:
check_dsp_r2(ctx);
@@ -12002,35 +12002,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_ADDQ_PW:
check_dsp(ctx);
- gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_PW:
check_dsp(ctx);
- gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_QH:
check_dsp(ctx);
- gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDQ_S_QH:
check_dsp(ctx);
- gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_OB:
check_dsp(ctx);
- gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_OB:
check_dsp(ctx);
- gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_QH:
check_dsp_r2(ctx);
- gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDU_S_QH:
check_dsp_r2(ctx);
- gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_ADDUH_OB:
check_dsp_r2(ctx);
@@ -12076,11 +12076,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
case OPC_PRECRQ_RS_QH_PW:
check_dsp(ctx);
- gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PRECRQU_S_OB_QH:
check_dsp(ctx);
- gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -12116,35 +12116,35 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
switch (op2) {
case OPC_SHLL_QB:
check_dsp(ctx);
- gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_QB:
check_dsp(ctx);
- gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_PH:
check_dsp(ctx);
- gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_PH:
check_dsp(ctx);
- gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_S_PH:
check_dsp(ctx);
- gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_S_PH:
check_dsp(ctx);
- gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHLL_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
+ gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env);
break;
case OPC_SHLLV_S_W:
check_dsp(ctx);
- gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_SHRL_QB:
check_dsp(ctx);
@@ -12215,43 +12215,43 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
switch (op2) {
case OPC_SHLL_PW:
check_dsp(ctx);
- gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_PW:
check_dsp(ctx);
- gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_S_PW:
check_dsp(ctx);
- gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_S_PW:
check_dsp(ctx);
- gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_OB:
check_dsp(ctx);
- gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_OB:
check_dsp(ctx);
- gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_QH:
check_dsp(ctx);
- gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_QH:
check_dsp(ctx);
- gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHLL_S_QH:
check_dsp(ctx);
- gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
+ gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
break;
case OPC_SHLLV_S_QH:
check_dsp(ctx);
- gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
+ gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
break;
case OPC_SHRA_OB:
check_dsp_r2(ctx);
@@ -12356,16 +12356,16 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
- gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MUL_S_PH:
- gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_S_W:
- gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_W:
- gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -12373,91 +12373,91 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_DPAU_H_QBL:
check_dsp(ctx);
- gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAU_H_QBR:
check_dsp(ctx);
- gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSU_H_QBL:
check_dsp(ctx);
- gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSU_H_QBR:
check_dsp(ctx);
- gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPS_W_PH:
check_dsp_r2(ctx);
- gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSX_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQ_S_W_PH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQX_S_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQX_SA_W_PH:
check_dsp_r2(ctx);
- gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MULSAQ_S_W_PH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPAQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env);
break;
case OPC_DPSQ_SA_L_W:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
+ gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_SA_W_PHL:
check_dsp(ctx);
- gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MAQ_SA_W_PHR:
check_dsp(ctx);
- gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
+ gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env);
break;
case OPC_MULSA_W_PH:
check_dsp_r2(ctx);
- gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
+ gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env);
break;
}
break;
@@ -12470,107 +12470,107 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_DMADD:
check_dsp(ctx);
- gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmadd(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMADDU:
check_dsp(ctx);
- gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMSUB:
check_dsp(ctx);
- gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmsub(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DMSUBU:
check_dsp(ctx);
- gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPA_W_QH:
check_dsp_r2(ctx);
- gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAQ_S_W_QH:
check_dsp(ctx);
- gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAQ_SA_L_PW:
check_dsp(ctx);
- gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAU_H_OBL:
check_dsp(ctx);
- gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPAU_H_OBR:
check_dsp(ctx);
- gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPS_W_QH:
check_dsp_r2(ctx);
- gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSQ_S_W_QH:
check_dsp(ctx);
- gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSQ_SA_L_PW:
check_dsp(ctx);
- gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSU_H_OBL:
check_dsp(ctx);
- gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_DPSU_H_OBR:
check_dsp(ctx);
- gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_L_PWL:
check_dsp(ctx);
- gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_L_PWR:
check_dsp(ctx);
- gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHLL:
check_dsp(ctx);
- gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHLL:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHLR:
check_dsp(ctx);
- gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHLR:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHRL:
check_dsp(ctx);
- gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHRL:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_S_W_QHRR:
check_dsp(ctx);
- gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MAQ_SA_W_QHRR:
check_dsp(ctx);
- gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
+ gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MULSAQ_S_L_PW:
check_dsp(ctx);
- gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
+ gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env);
break;
case OPC_MULSAQ_S_W_QH:
check_dsp(ctx);
- gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
+ gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
break;
}
}
@@ -12580,27 +12580,27 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_MULEU_S_PH_QBL:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_PH_QBR:
check_dsp(ctx);
- gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_PH:
check_dsp(ctx);
- gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_W_PHL:
check_dsp(ctx);
- gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_W_PHR:
check_dsp(ctx);
- gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_S_PH:
check_dsp_r2(ctx);
- gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -12609,23 +12609,23 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_MULEQ_S_PW_QHL:
check_dsp(ctx);
- gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEQ_S_PW_QHR:
check_dsp(ctx);
- gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_QH_OBL:
check_dsp(ctx);
- gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULEU_S_QH_OBR:
check_dsp(ctx);
- gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_MULQ_RS_QH:
check_dsp(ctx);
- gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -12794,15 +12794,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
switch (op2) {
case OPC_CMPU_EQ_QB:
check_dsp(ctx);
- gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LT_QB:
check_dsp(ctx);
- gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LE_QB:
check_dsp(ctx);
- gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
break;
case OPC_CMPGU_EQ_QB:
check_dsp(ctx);
@@ -12842,23 +12842,23 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
break;
case OPC_CMP_EQ_PH:
check_dsp(ctx);
- gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_PH:
check_dsp(ctx);
- gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_PH:
check_dsp(ctx);
- gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
break;
case OPC_PICK_QB:
check_dsp(ctx);
- gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_PH:
check_dsp(ctx);
- gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PACKRL_PH:
check_dsp(ctx);
@@ -12871,39 +12871,39 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
switch (op2) {
case OPC_CMP_EQ_PW:
check_dsp(ctx);
- gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_PW:
check_dsp(ctx);
- gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_PW:
check_dsp(ctx);
- gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_EQ_QH:
check_dsp(ctx);
- gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LT_QH:
check_dsp(ctx);
- gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMP_LE_QH:
check_dsp(ctx);
- gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
+ gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_EQ_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_LT_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGDU_LE_OB:
check_dsp_r2(ctx);
- gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_CMPGU_EQ_OB:
check_dsp(ctx);
@@ -12919,15 +12919,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
break;
case OPC_CMPU_EQ_OB:
check_dsp(ctx);
- gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LT_OB:
check_dsp(ctx);
- gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env);
break;
case OPC_CMPU_LE_OB:
check_dsp(ctx);
- gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
+ gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env);
break;
case OPC_PACKRL_PW:
check_dsp(ctx);
@@ -12935,15 +12935,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
break;
case OPC_PICK_OB:
check_dsp(ctx);
- gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_PW:
check_dsp(ctx);
- gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
case OPC_PICK_QH:
check_dsp(ctx);
- gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
+ gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
break;
}
break;
@@ -13065,80 +13065,80 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_EXTR_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_R_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_RS_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTR_S_H:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_R_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTRV_RS_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_EXTPDP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_EXTPDPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_SHILO:
imm = (ctx->opcode >> 20) & 0x3F;
tcg_gen_movi_tl(t0, ret);
tcg_gen_movi_tl(t1, imm);
- gen_helper_shilo(t0, t1, cpu_env);
+ gen_helper_shilo(t0, t1, tcg_env);
break;
case OPC_SHILOV:
tcg_gen_movi_tl(t0, ret);
- gen_helper_shilo(t0, v1_t, cpu_env);
+ gen_helper_shilo(t0, v1_t, tcg_env);
break;
case OPC_MTHLIP:
tcg_gen_movi_tl(t0, ret);
- gen_helper_mthlip(t0, v1_t, cpu_env);
+ gen_helper_mthlip(t0, v1_t, tcg_env);
break;
case OPC_WRDSP:
imm = (ctx->opcode >> 11) & 0x3FF;
tcg_gen_movi_tl(t0, imm);
- gen_helper_wrdsp(v1_t, t0, cpu_env);
+ gen_helper_wrdsp(v1_t, t0, tcg_env);
break;
case OPC_RDDSP:
imm = (ctx->opcode >> 16) & 0x03FF;
tcg_gen_movi_tl(t0, imm);
- gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
+ gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env);
break;
}
break;
@@ -13148,7 +13148,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op2) {
case OPC_DMTHLIP:
tcg_gen_movi_tl(t0, ret);
- gen_helper_dmthlip(v1_t, t0, cpu_env);
+ gen_helper_dmthlip(v1_t, t0, tcg_env);
break;
case OPC_DSHILO:
{
@@ -13156,97 +13156,97 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
int ac = (ctx->opcode >> 11) & 0x03;
tcg_gen_movi_tl(t0, shift);
tcg_gen_movi_tl(t1, ac);
- gen_helper_dshilo(t0, t1, cpu_env);
+ gen_helper_dshilo(t0, t1, tcg_env);
break;
}
case OPC_DSHILOV:
{
int ac = (ctx->opcode >> 11) & 0x03;
tcg_gen_movi_tl(t0, ac);
- gen_helper_dshilo(v1_t, t0, cpu_env);
+ gen_helper_dshilo(v1_t, t0, tcg_env);
break;
}
case OPC_DEXTP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTPDP:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTPDPV:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTR_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_R_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_RS_L:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_R_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_RS_W:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTR_S_H:
tcg_gen_movi_tl(t0, v2);
tcg_gen_movi_tl(t1, v1);
- gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
+ gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
break;
case OPC_DEXTRV_S_H:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_R_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_RS_L:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_R_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
case OPC_DEXTRV_RS_W:
tcg_gen_movi_tl(t0, v2);
- gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
+ gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
break;
}
break;
@@ -13578,7 +13578,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
- gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
+ gen_helper_pmon(tcg_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL:
@@ -14101,7 +14101,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
+ gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0);
break;
}
default: /* Invalid */
@@ -14370,7 +14370,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
+ gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0);
break;
}
default: /* Invalid */
@@ -14605,7 +14605,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs);
- gen_helper_yield(t0, cpu_env, t0);
+ gen_helper_yield(t0, tcg_env, t0);
gen_store_gpr(t0, rd);
}
break;
@@ -14796,32 +14796,32 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DVPE:
check_cp0_mt(ctx);
- gen_helper_dvpe(t0, cpu_env);
+ gen_helper_dvpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_cp0_mt(ctx);
- gen_helper_evpe(t0, cpu_env);
+ gen_helper_evpe(t0, tcg_env);
gen_store_gpr(t0, rt);
break;
case OPC_DVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
- gen_helper_dvp(t0, cpu_env);
+ gen_helper_dvp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_EVP:
check_insn(ctx, ISA_MIPS_R6);
if (ctx->vp) {
- gen_helper_evp(t0, cpu_env);
+ gen_helper_evp(t0, tcg_env);
gen_store_gpr(t0, rt);
}
break;
case OPC_DI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
- gen_helper_di(t0, cpu_env);
+ gen_helper_di(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* Stop translation as we may have switched
@@ -14832,7 +14832,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_EI:
check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
- gen_helper_ei(t0, cpu_env);
+ gen_helper_ei(t0, tcg_env);
gen_store_gpr(t0, rt);
/*
* DISAS_STOP isn't sufficient, we need to ensure we break
@@ -15565,7 +15565,7 @@ void mips_tcg_init(void)
{
cpu_gpr[0] = NULL;
for (unsigned i = 1; i < 32; i++)
- cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+ cpu_gpr[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
@@ -15575,7 +15575,7 @@ void mips_tcg_init(void)
for (unsigned i = 1; i < 32; i++) {
g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
- cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
+ cpu_gpr_hi[i] = tcg_global_mem_new_i64(tcg_env,
offsetof(CPUMIPSState,
active_tc.gpr_hi[i]),
rname);
@@ -15584,39 +15584,39 @@ void mips_tcg_init(void)
for (unsigned i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ fpu_f64[i] = tcg_global_mem_new_i64(tcg_env, off, fregnames[i]);
}
msa_translate_init();
- cpu_PC = tcg_global_mem_new(cpu_env,
+ cpu_PC = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (unsigned i = 0; i < MIPS_DSP_ACC; i++) {
- cpu_HI[i] = tcg_global_mem_new(cpu_env,
+ cpu_HI[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.HI[i]),
regnames_HI[i]);
- cpu_LO[i] = tcg_global_mem_new(cpu_env,
+ cpu_LO[i] = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
}
- cpu_dspctrl = tcg_global_mem_new(cpu_env,
+ cpu_dspctrl = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState,
active_tc.DSPControl),
"DSPControl");
- bcond = tcg_global_mem_new(cpu_env,
+ bcond = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, bcond), "bcond");
- btarget = tcg_global_mem_new(cpu_env,
+ btarget = tcg_global_mem_new(tcg_env,
offsetof(CPUMIPSState, btarget), "btarget");
- hflags = tcg_global_mem_new_i32(cpu_env,
+ hflags = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, hflags), "hflags");
- fpu_fcr0 = tcg_global_mem_new_i32(cpu_env,
+ fpu_fcr0 = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, active_fpu.fcr0),
"fcr0");
- fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
+ fpu_fcr31 = tcg_global_mem_new_i32(tcg_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
- cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr),
+ cpu_lladdr = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, lladdr),
"lladdr");
- cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
+ cpu_llval = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval),
"llval");
if (TARGET_LONG_BITS == 32) {
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index db3dc932c7..cffcfeab8c 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -123,15 +123,15 @@ enum {
};
#define gen_helper_0e1i(name, arg1, arg2) do { \
- gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \
+ gen_helper_##name(tcg_env, arg1, tcg_constant_i32(arg2)); \
} while (0)
#define gen_helper_1e0i(name, ret, arg1) do { \
- gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \
+ gen_helper_##name(ret, tcg_env, tcg_constant_i32(arg1)); \
} while (0)
#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
- gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\
+ gen_helper_##name(tcg_env, arg1, arg2, tcg_constant_i32(arg3));\
} while (0)
void generate_exception(DisasContext *ctx, int excp);
diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c
index 2c1f6cc527..c877ede76e 100644
--- a/target/mips/tcg/vr54xx_translate.c
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -43,7 +43,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
- gen_helper_mult_acc(t0, cpu_env, t0, t1);
+ gen_helper_mult_acc(t0, tcg_env, t0, t1);
gen_store_gpr(t0, a->rd);
return true;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-22 15:08:17 +0000