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authorRichard Henderson <richard.henderson@linaro.org>2021-02-27 12:44:00 -0800
committerRichard Henderson <richard.henderson@linaro.org>2021-05-26 15:33:59 -0700
commit3803b6b4273afd50021c39a8e34ca706aeadb684 (patch)
treec953b24f4dd1409f1a395481f7174f2c0b9eca34 /target/mips
parent6bc0d6a04733cb39d2d2bf3380a857709113242f (diff)
target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/cpu-qom.h3
-rw-r--r--target/mips/tcg/op_helper.c3
2 files changed, 5 insertions, 1 deletions
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 826ab13019..dda0c911fa 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -47,6 +47,9 @@ struct MIPSCPUClass {
DeviceRealize parent_realize;
DeviceReset parent_reset;
const struct mips_def_t *cpu_def;
+
+ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
+ bool no_data_aborts;
};
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index ce1549c985..fafbf1faca 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env;
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
- } else {
+ } else if (!mcc->no_data_aborts) {
do_raise_exception(env, EXCP_DBE, retaddr);
}
}