diff options
author | Emilio G. Cota <cota@braap.org> | 2017-07-18 20:46:52 -0400 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2017-10-24 13:53:41 -0700 |
commit | c5a49c63fa26e8825ad101dfe86339ae4c216539 (patch) | |
tree | c41e1a7064e88f65292a3b09684123f9f499617e /target/mips | |
parent | cdfef1715c779eb528d633e8b76cbc8a10e71ac8 (diff) |
tcg: convert tb->cflags reads to tb_cflags(tb)
Convert all existing readers of tb->cflags to tb_cflags, so that we
use atomic_read and therefore avoid undefined behaviour in C11.
Note that the remaining setters/getters of the field are protected
by tb_lock, and therefore do not need conversion.
Luckily all readers access the field via 'tb->cflags' (so no foo.cflags,
bar->cflags in the code base), which makes the conversion easily
scriptable:
FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \
accel/tcg/translator.c | cut -f1 -d':' | sort | uniq)
perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES
perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES
Then manually fixed the few errors that checkpatch reported.
Compile-tested for all targets.
Suggested-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r-- | target/mips/translate.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index ef07fa827e..aadffbec39 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5327,11 +5327,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5734,7 +5734,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS32); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6401,7 +6401,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("mtc0", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -6679,11 +6679,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -7072,7 +7072,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS64); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -7727,7 +7727,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("dmtc0", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -10756,11 +10756,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 2: - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdhwr_cc(t0, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_store_gpr(t0, rt); @@ -20248,7 +20248,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; + max_insns = tb_cflags(tb) & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } @@ -20274,7 +20274,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) goto done_generating; } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } @@ -20335,7 +20335,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (singlestep) break; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) { |