aboutsummaryrefslogtreecommitdiff
path: root/target/mips
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2021-06-13 16:27:13 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-06-29 10:04:57 -0700
commit92ecfab50ee2b30e60c774f96f05fc38714874f1 (patch)
tree07407b0c1a10d8abaa3c1ac8ccd90d3f27a30a23 /target/mips
parentb983a0e17240fcbc8e1a32ef44221a1954332c81 (diff)
target/mips: Fix gen_mxu_s32ldd_s32lddr
There were two bugs here: (1) the required endianness was not present in the MemOp, and (2) we were not providing a zero-extended input to the bswap as semantics required. The best fix is to fold the bswap into the memory operation, producing the desired result directly. Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/tcg/mxu_translate.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 3f35e46399..f52244e1b2 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -857,12 +857,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
}
tcg_gen_add_tl(t1, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
+ tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
- if (sel == 1) {
- /* S32LDDR */
- tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
gen_store_mxu_gpr(t1, XRa);
tcg_temp_free(t0);