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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-04-21 20:39:15 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-02 16:49:34 +0200 |
| commit | 298d43c96b0f7dc7ea6550ea73b128b3d4ed67f9 (patch) | |
| tree | ea6978eb693ae02460b7f78bfdfd1047136c9d15 /target/mips | |
| parent | 84c2fdc397b6609d1cef76aec2f1367139d1372e (diff) | |
target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":
The Read/Write Previous GPR opcodes "require CP0 privilege".
Add the missing CP0 checks.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 5dad75cdf3..8a0a219742 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -18969,9 +18969,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } break; case NM_RDPGPR: + check_cp0_enabled(ctx); gen_load_srsgpr(rs, rt); break; case NM_WRPGPR: + check_cp0_enabled(ctx); gen_store_srsgpr(rs, rt); break; case NM_WAIT: |