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authorCraig Janeczek <jancraig@amazon.com>2018-10-19 17:49:19 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2018-10-29 14:13:53 +0100
commit11d56f61036091206f085e58cff72b6872911d3a (patch)
tree0bce6eb854cb74d009a42abba49d4be9df147acd /target/mips
parent53f1131fde02ae49e1f794f811a60fda32c72dca (diff)
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Add emulation of non-MXU MULL within MXU decoding engine. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/translate.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ccabd13c94..bdd46ed49c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1648,7 +1648,7 @@ enum {
enum {
OPC_MXU_S32MADD = 0x00,
OPC_MXU_S32MADDU = 0x01,
- /* not assigned 0x02 */
+ OPC__MXU_MUL = 0x02,
OPC_MXU__POOL00 = 0x03,
OPC_MXU_S32MSUB = 0x04,
OPC_MXU_S32MSUBU = 0x05,
@@ -24909,6 +24909,11 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
*/
static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
{
+ /*
+ * TODO: Investigate necessity of including handling of
+ * CLZ, CLO, SDBB in this function, as they belong to
+ * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
+ */
uint32_t opcode = extract32(ctx->opcode, 0, 6);
switch (opcode) {
@@ -24922,6 +24927,18 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
+ case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
+ {
+ uint32_t rs, rt, rd, op1;
+
+ rs = extract32(ctx->opcode, 21, 5);
+ rt = extract32(ctx->opcode, 16, 5);
+ rd = extract32(ctx->opcode, 11, 5);
+ op1 = MASK_SPECIAL2(ctx->opcode);
+
+ gen_arith(ctx, op1, rd, rs, rt);
+ }
+ break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;