diff options
| author | Laurent Vivier <laurent@vivier.eu> | 2018-01-18 20:38:40 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2018-01-25 16:02:24 +0100 |
| commit | 98670d47cd8d63a529ff230fd39ddaa186156f8c (patch) | |
| tree | ce2092bb342d6350919eb1fbad02dfdd446a4123 /target/mips | |
| parent | 39e3e113bdb27b4144d697fbd6678a9c24740103 (diff) | |
accel/tcg: add size paremeter in tlb_fill()
The MC68040 MMU provides the size of the access that
triggers the page fault.
This size is set in the Special Status Word which
is written in the stack frame of the access fault
exception.
So we need the size in m68k_cpu_unassigned_access() and
m68k_cpu_handle_mmu_fault().
To be able to do that, this patch modifies the prototype of
handle_mmu_fault handler, tlb_fill() and probe_write().
do_unassigned_access() already includes a size parameter.
This patch also updates handle_mmu_fault handlers and
tlb_fill() of all targets (only parameter, no code change).
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/helper.c | 2 | ||||
| -rw-r--r-- | target/mips/internal.h | 2 | ||||
| -rw-r--r-- | target/mips/op_helper.c | 10 |
3 files changed, 7 insertions, 7 deletions
diff --git a/target/mips/helper.c b/target/mips/helper.c index ea076261af..8cf91ce339 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -535,7 +535,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } #endif -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, +int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { MIPSCPU *cpu = MIPS_CPU(cs); diff --git a/target/mips/internal.h b/target/mips/internal.h index 45ded3484c..e41051f8e6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -202,7 +202,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); /* op_helper.c */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e537a8bfd8..798cdad030 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2451,12 +2451,12 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; - ret = mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); if (ret) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; @@ -4190,10 +4190,10 @@ static inline void ensure_writable_pages(CPUMIPSState *env, target_ulong page_addr; if (unlikely(MSA_PAGESPAN(addr))) { /* first page */ - probe_write(env, addr, mmu_idx, retaddr); + probe_write(env, addr, 0, mmu_idx, retaddr); /* second page */ page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, page_addr, mmu_idx, retaddr); + probe_write(env, page_addr, 0, mmu_idx, retaddr); } #endif } |