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authorzhaolichang <zhaolichang@huawei.com>2020-10-09 14:44:41 +0800
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-17 11:08:42 +0200
commit8cdf88690dc79511cfa1b2557434c09e3685f090 (patch)
tree853b6d1cb9f7d0f986375ca18c8cf60854057446 /target/mips/translate_init.c.inc
parent5ebc664800b66f886f58cd4d5bcc7785644c9980 (diff)
target/mips: Fix some comment spelling errors
There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/translate_init.c.inc')
-rw-r--r--target/mips/translate_init.c.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637caccd89..c735b2bf66 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
- and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
+ and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |