diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-08 18:55:47 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | a685f7d075a7ec09575cbb836cf07b64ae313e30 (patch) | |
| tree | 13b583d6ef2a085cd1b610cc98beeb6b11234cad /target/mips/translate.h | |
| parent | 96e5b4c7584d623f6cdcb0083829c19141b2b130 (diff) | |
target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
Diffstat (limited to 'target/mips/translate.h')
| -rw-r--r-- | target/mips/translate.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/mips/translate.h b/target/mips/translate.h index 9b38f82ecd..f93df0c5ab 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -137,7 +137,12 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); int get_fp_bit(int cc); +/* + * Address Computation and Large Constant Instructions + */ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); +bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); +bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; extern TCGv_i32 fpu_fcr0, fpu_fcr31; |